Core Register type definitions. More...
Topics | |
| Nested Vectored Interrupt Controller (NVIC) | |
| Type definitions for the NVIC Registers. | |
Data Structures | |
| union | APSR_Type |
| Union type to access the Application Program Status Register (APSR). More... | |
| union | IPSR_Type |
| Union type to access the Interrupt Program Status Register (IPSR). More... | |
| union | xPSR_Type |
| Union type to access the Special-Purpose Program Status Registers (xPSR). More... | |
| union | CONTROL_Type |
| Union type to access the Control Registers (CONTROL). More... | |
| struct | APSR_Type.b |
| struct | IPSR_Type.b |
| struct | xPSR_Type.b |
| struct | CONTROL_Type.b |
Core Register type definitions.
| union APSR_Type |
Union type to access the Application Program Status Register (APSR).
Definition at line 328 of file core_armv81mml.h.
| union IPSR_Type |
Union type to access the Interrupt Program Status Register (IPSR).
Definition at line 367 of file core_armv81mml.h.
| union xPSR_Type |
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition at line 385 of file core_armv81mml.h.
| union CONTROL_Type |
Union type to access the Control Registers (CONTROL).
Definition at line 436 of file core_armv81mml.h.
| struct APSR_Type.b |
Definition at line 329 of file core_starmc1.h.
| struct IPSR_Type.b |
Definition at line 368 of file core_starmc1.h.
| struct xPSR_Type.b |
Definition at line 386 of file core_starmc1.h.
| struct CONTROL_Type.b |
Definition at line 437 of file core_starmc1.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 345 of file core_armv81mml.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 346 of file core_armv81mml.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 348 of file core_armv81mml.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 349 of file core_armv81mml.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 351 of file core_armv81mml.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 352 of file core_armv81mml.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 354 of file core_armv81mml.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 355 of file core_armv81mml.h.
| #define APSR_Q_Pos 27U |
APSR: Q Position
Definition at line 357 of file core_armv81mml.h.
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
Definition at line 358 of file core_armv81mml.h.
| #define APSR_GE_Pos 16U |
APSR: GE Position
Definition at line 360 of file core_armv81mml.h.
| #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) |
APSR: GE Mask
Definition at line 361 of file core_armv81mml.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 378 of file core_armv81mml.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 379 of file core_armv81mml.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 405 of file core_armv81mml.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 406 of file core_armv81mml.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 408 of file core_armv81mml.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 409 of file core_armv81mml.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 411 of file core_armv81mml.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 412 of file core_armv81mml.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 414 of file core_armv81mml.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 415 of file core_armv81mml.h.
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
Definition at line 417 of file core_armv81mml.h.
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
Definition at line 418 of file core_armv81mml.h.
| #define xPSR_IT_Pos 25U |
xPSR: IT Position
Definition at line 420 of file core_armv81mml.h.
| #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) |
xPSR: IT Mask
Definition at line 421 of file core_armv81mml.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 423 of file core_armv81mml.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 424 of file core_armv81mml.h.
| #define xPSR_GE_Pos 16U |
xPSR: GE Position
Definition at line 426 of file core_armv81mml.h.
| #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) |
xPSR: GE Mask
Definition at line 427 of file core_armv81mml.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 429 of file core_armv81mml.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 430 of file core_armv81mml.h.
| #define CONTROL_SFPA_Pos 3U |
CONTROL: SFPA Position
Definition at line 450 of file core_armv81mml.h.
| #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) |
CONTROL: SFPA Mask
Definition at line 451 of file core_armv81mml.h.
| #define CONTROL_FPCA_Pos 2U |
CONTROL: FPCA Position
Definition at line 453 of file core_armv81mml.h.
| #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) |
CONTROL: FPCA Mask
Definition at line 454 of file core_armv81mml.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 456 of file core_armv81mml.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 457 of file core_armv81mml.h.
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
Definition at line 459 of file core_armv81mml.h.
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
Definition at line 460 of file core_armv81mml.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 249 of file core_armv8mbl.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 250 of file core_armv8mbl.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 252 of file core_armv8mbl.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 253 of file core_armv8mbl.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 255 of file core_armv8mbl.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 256 of file core_armv8mbl.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 258 of file core_armv8mbl.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 259 of file core_armv8mbl.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 276 of file core_armv8mbl.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 277 of file core_armv8mbl.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 300 of file core_armv8mbl.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 301 of file core_armv8mbl.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 303 of file core_armv8mbl.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 304 of file core_armv8mbl.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 306 of file core_armv8mbl.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 307 of file core_armv8mbl.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 309 of file core_armv8mbl.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 310 of file core_armv8mbl.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 312 of file core_armv8mbl.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 313 of file core_armv8mbl.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 315 of file core_armv8mbl.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 316 of file core_armv8mbl.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 334 of file core_armv8mbl.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 335 of file core_armv8mbl.h.
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
Definition at line 337 of file core_armv8mbl.h.
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
Definition at line 338 of file core_armv8mbl.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 338 of file core_armv8mml.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 339 of file core_armv8mml.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 341 of file core_armv8mml.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 342 of file core_armv8mml.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 344 of file core_armv8mml.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 345 of file core_armv8mml.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 347 of file core_armv8mml.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 348 of file core_armv8mml.h.
| #define APSR_Q_Pos 27U |
APSR: Q Position
Definition at line 350 of file core_armv8mml.h.
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
Definition at line 351 of file core_armv8mml.h.
| #define APSR_GE_Pos 16U |
APSR: GE Position
Definition at line 353 of file core_armv8mml.h.
| #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) |
APSR: GE Mask
Definition at line 354 of file core_armv8mml.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 371 of file core_armv8mml.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 372 of file core_armv8mml.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 398 of file core_armv8mml.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 399 of file core_armv8mml.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 401 of file core_armv8mml.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 402 of file core_armv8mml.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 404 of file core_armv8mml.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 405 of file core_armv8mml.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 407 of file core_armv8mml.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 408 of file core_armv8mml.h.
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
Definition at line 410 of file core_armv8mml.h.
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
Definition at line 411 of file core_armv8mml.h.
| #define xPSR_IT_Pos 25U |
xPSR: IT Position
Definition at line 413 of file core_armv8mml.h.
| #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) |
xPSR: IT Mask
Definition at line 414 of file core_armv8mml.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 416 of file core_armv8mml.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 417 of file core_armv8mml.h.
| #define xPSR_GE_Pos 16U |
xPSR: GE Position
Definition at line 419 of file core_armv8mml.h.
| #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) |
xPSR: GE Mask
Definition at line 420 of file core_armv8mml.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 422 of file core_armv8mml.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 423 of file core_armv8mml.h.
| #define CONTROL_SFPA_Pos 3U |
CONTROL: SFPA Position
Definition at line 443 of file core_armv8mml.h.
| #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) |
CONTROL: SFPA Mask
Definition at line 444 of file core_armv8mml.h.
| #define CONTROL_FPCA_Pos 2U |
CONTROL: FPCA Position
Definition at line 446 of file core_armv8mml.h.
| #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) |
CONTROL: FPCA Mask
Definition at line 447 of file core_armv8mml.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 449 of file core_armv8mml.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 450 of file core_armv8mml.h.
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
Definition at line 452 of file core_armv8mml.h.
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
Definition at line 453 of file core_armv8mml.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 213 of file core_cm0.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 214 of file core_cm0.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 216 of file core_cm0.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 217 of file core_cm0.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 219 of file core_cm0.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 220 of file core_cm0.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 222 of file core_cm0.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 223 of file core_cm0.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 240 of file core_cm0.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 241 of file core_cm0.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 264 of file core_cm0.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 265 of file core_cm0.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 267 of file core_cm0.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 268 of file core_cm0.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 270 of file core_cm0.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 271 of file core_cm0.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 273 of file core_cm0.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 274 of file core_cm0.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 276 of file core_cm0.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 277 of file core_cm0.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 279 of file core_cm0.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 280 of file core_cm0.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 298 of file core_cm0.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 299 of file core_cm0.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 224 of file core_cm0plus.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 225 of file core_cm0plus.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 227 of file core_cm0plus.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 228 of file core_cm0plus.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 230 of file core_cm0plus.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 231 of file core_cm0plus.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 233 of file core_cm0plus.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 234 of file core_cm0plus.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 251 of file core_cm0plus.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 252 of file core_cm0plus.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 275 of file core_cm0plus.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 276 of file core_cm0plus.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 278 of file core_cm0plus.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 279 of file core_cm0plus.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 281 of file core_cm0plus.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 282 of file core_cm0plus.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 284 of file core_cm0plus.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 285 of file core_cm0plus.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 287 of file core_cm0plus.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 288 of file core_cm0plus.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 290 of file core_cm0plus.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 291 of file core_cm0plus.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 309 of file core_cm0plus.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 310 of file core_cm0plus.h.
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
Definition at line 312 of file core_cm0plus.h.
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
Definition at line 313 of file core_cm0plus.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 213 of file core_cm1.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 214 of file core_cm1.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 216 of file core_cm1.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 217 of file core_cm1.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 219 of file core_cm1.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 220 of file core_cm1.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 222 of file core_cm1.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 223 of file core_cm1.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 240 of file core_cm1.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 241 of file core_cm1.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 264 of file core_cm1.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 265 of file core_cm1.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 267 of file core_cm1.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 268 of file core_cm1.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 270 of file core_cm1.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 271 of file core_cm1.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 273 of file core_cm1.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 274 of file core_cm1.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 276 of file core_cm1.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 277 of file core_cm1.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 279 of file core_cm1.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 280 of file core_cm1.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 298 of file core_cm1.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 299 of file core_cm1.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 249 of file core_cm23.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 250 of file core_cm23.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 252 of file core_cm23.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 253 of file core_cm23.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 255 of file core_cm23.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 256 of file core_cm23.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 258 of file core_cm23.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 259 of file core_cm23.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 276 of file core_cm23.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 277 of file core_cm23.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 300 of file core_cm23.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 301 of file core_cm23.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 303 of file core_cm23.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 304 of file core_cm23.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 306 of file core_cm23.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 307 of file core_cm23.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 309 of file core_cm23.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 310 of file core_cm23.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 312 of file core_cm23.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 313 of file core_cm23.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 315 of file core_cm23.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 316 of file core_cm23.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 334 of file core_cm23.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 335 of file core_cm23.h.
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
Definition at line 337 of file core_cm23.h.
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
Definition at line 338 of file core_cm23.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 226 of file core_cm3.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 227 of file core_cm3.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 229 of file core_cm3.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 230 of file core_cm3.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 232 of file core_cm3.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 233 of file core_cm3.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 235 of file core_cm3.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 236 of file core_cm3.h.
| #define APSR_Q_Pos 27U |
APSR: Q Position
Definition at line 238 of file core_cm3.h.
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
Definition at line 239 of file core_cm3.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 256 of file core_cm3.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 257 of file core_cm3.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 283 of file core_cm3.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 284 of file core_cm3.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 286 of file core_cm3.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 287 of file core_cm3.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 289 of file core_cm3.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 290 of file core_cm3.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 292 of file core_cm3.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 293 of file core_cm3.h.
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
Definition at line 295 of file core_cm3.h.
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
Definition at line 296 of file core_cm3.h.
| #define xPSR_ICI_IT_2_Pos 25U |
xPSR: ICI/IT part 2 Position
Definition at line 298 of file core_cm3.h.
| #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) |
xPSR: ICI/IT part 2 Mask
Definition at line 299 of file core_cm3.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 301 of file core_cm3.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 302 of file core_cm3.h.
| #define xPSR_ICI_IT_1_Pos 10U |
xPSR: ICI/IT part 1 Position
Definition at line 304 of file core_cm3.h.
| #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) |
xPSR: ICI/IT part 1 Mask
Definition at line 305 of file core_cm3.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 307 of file core_cm3.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 308 of file core_cm3.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 326 of file core_cm3.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 327 of file core_cm3.h.
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
Definition at line 329 of file core_cm3.h.
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
Definition at line 330 of file core_cm3.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 338 of file core_cm33.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 339 of file core_cm33.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 341 of file core_cm33.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 342 of file core_cm33.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 344 of file core_cm33.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 345 of file core_cm33.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 347 of file core_cm33.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 348 of file core_cm33.h.
| #define APSR_Q_Pos 27U |
APSR: Q Position
Definition at line 350 of file core_cm33.h.
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
Definition at line 351 of file core_cm33.h.
| #define APSR_GE_Pos 16U |
APSR: GE Position
Definition at line 353 of file core_cm33.h.
| #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) |
APSR: GE Mask
Definition at line 354 of file core_cm33.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 371 of file core_cm33.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 372 of file core_cm33.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 398 of file core_cm33.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 399 of file core_cm33.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 401 of file core_cm33.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 402 of file core_cm33.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 404 of file core_cm33.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 405 of file core_cm33.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 407 of file core_cm33.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 408 of file core_cm33.h.
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
Definition at line 410 of file core_cm33.h.
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
Definition at line 411 of file core_cm33.h.
| #define xPSR_IT_Pos 25U |
xPSR: IT Position
Definition at line 413 of file core_cm33.h.
| #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) |
xPSR: IT Mask
Definition at line 414 of file core_cm33.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 416 of file core_cm33.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 417 of file core_cm33.h.
| #define xPSR_GE_Pos 16U |
xPSR: GE Position
Definition at line 419 of file core_cm33.h.
| #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) |
xPSR: GE Mask
Definition at line 420 of file core_cm33.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 422 of file core_cm33.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 423 of file core_cm33.h.
| #define CONTROL_SFPA_Pos 3U |
CONTROL: SFPA Position
Definition at line 443 of file core_cm33.h.
| #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) |
CONTROL: SFPA Mask
Definition at line 444 of file core_cm33.h.
| #define CONTROL_FPCA_Pos 2U |
CONTROL: FPCA Position
Definition at line 446 of file core_cm33.h.
| #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) |
CONTROL: FPCA Mask
Definition at line 447 of file core_cm33.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 449 of file core_cm33.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 450 of file core_cm33.h.
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
Definition at line 452 of file core_cm33.h.
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
Definition at line 453 of file core_cm33.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 338 of file core_cm35p.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 339 of file core_cm35p.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 341 of file core_cm35p.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 342 of file core_cm35p.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 344 of file core_cm35p.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 345 of file core_cm35p.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 347 of file core_cm35p.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 348 of file core_cm35p.h.
| #define APSR_Q_Pos 27U |
APSR: Q Position
Definition at line 350 of file core_cm35p.h.
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
Definition at line 351 of file core_cm35p.h.
| #define APSR_GE_Pos 16U |
APSR: GE Position
Definition at line 353 of file core_cm35p.h.
| #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) |
APSR: GE Mask
Definition at line 354 of file core_cm35p.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 371 of file core_cm35p.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 372 of file core_cm35p.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 398 of file core_cm35p.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 399 of file core_cm35p.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 401 of file core_cm35p.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 402 of file core_cm35p.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 404 of file core_cm35p.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 405 of file core_cm35p.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 407 of file core_cm35p.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 408 of file core_cm35p.h.
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
Definition at line 410 of file core_cm35p.h.
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
Definition at line 411 of file core_cm35p.h.
| #define xPSR_IT_Pos 25U |
xPSR: IT Position
Definition at line 413 of file core_cm35p.h.
| #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) |
xPSR: IT Mask
Definition at line 414 of file core_cm35p.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 416 of file core_cm35p.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 417 of file core_cm35p.h.
| #define xPSR_GE_Pos 16U |
xPSR: GE Position
Definition at line 419 of file core_cm35p.h.
| #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) |
xPSR: GE Mask
Definition at line 420 of file core_cm35p.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 422 of file core_cm35p.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 423 of file core_cm35p.h.
| #define CONTROL_SFPA_Pos 3U |
CONTROL: SFPA Position
Definition at line 443 of file core_cm35p.h.
| #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) |
CONTROL: SFPA Mask
Definition at line 444 of file core_cm35p.h.
| #define CONTROL_FPCA_Pos 2U |
CONTROL: FPCA Position
Definition at line 446 of file core_cm35p.h.
| #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) |
CONTROL: FPCA Mask
Definition at line 447 of file core_cm35p.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 449 of file core_cm35p.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 450 of file core_cm35p.h.
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
Definition at line 452 of file core_cm35p.h.
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
Definition at line 453 of file core_cm35p.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 281 of file core_cm4.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 282 of file core_cm4.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 284 of file core_cm4.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 285 of file core_cm4.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 287 of file core_cm4.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 288 of file core_cm4.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 290 of file core_cm4.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 291 of file core_cm4.h.
| #define APSR_Q_Pos 27U |
APSR: Q Position
Definition at line 293 of file core_cm4.h.
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
Definition at line 294 of file core_cm4.h.
| #define APSR_GE_Pos 16U |
APSR: GE Position
Definition at line 296 of file core_cm4.h.
| #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) |
APSR: GE Mask
Definition at line 297 of file core_cm4.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 314 of file core_cm4.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 315 of file core_cm4.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 342 of file core_cm4.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 343 of file core_cm4.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 345 of file core_cm4.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 346 of file core_cm4.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 348 of file core_cm4.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 349 of file core_cm4.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 351 of file core_cm4.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 352 of file core_cm4.h.
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
Definition at line 354 of file core_cm4.h.
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
Definition at line 355 of file core_cm4.h.
| #define xPSR_ICI_IT_2_Pos 25U |
xPSR: ICI/IT part 2 Position
Definition at line 357 of file core_cm4.h.
| #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) |
xPSR: ICI/IT part 2 Mask
Definition at line 358 of file core_cm4.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 360 of file core_cm4.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 361 of file core_cm4.h.
| #define xPSR_GE_Pos 16U |
xPSR: GE Position
Definition at line 363 of file core_cm4.h.
| #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) |
xPSR: GE Mask
Definition at line 364 of file core_cm4.h.
| #define xPSR_ICI_IT_1_Pos 10U |
xPSR: ICI/IT part 1 Position
Definition at line 366 of file core_cm4.h.
| #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) |
xPSR: ICI/IT part 1 Mask
Definition at line 367 of file core_cm4.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 369 of file core_cm4.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 370 of file core_cm4.h.
| #define CONTROL_FPCA_Pos 2U |
CONTROL: FPCA Position
Definition at line 389 of file core_cm4.h.
| #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) |
CONTROL: FPCA Mask
Definition at line 390 of file core_cm4.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 392 of file core_cm4.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 393 of file core_cm4.h.
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
Definition at line 395 of file core_cm4.h.
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
Definition at line 396 of file core_cm4.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 347 of file core_cm55.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 348 of file core_cm55.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 350 of file core_cm55.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 351 of file core_cm55.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 353 of file core_cm55.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 354 of file core_cm55.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 356 of file core_cm55.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 357 of file core_cm55.h.
| #define APSR_Q_Pos 27U |
APSR: Q Position
Definition at line 359 of file core_cm55.h.
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
Definition at line 360 of file core_cm55.h.
| #define APSR_GE_Pos 16U |
APSR: GE Position
Definition at line 362 of file core_cm55.h.
| #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) |
APSR: GE Mask
Definition at line 363 of file core_cm55.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 380 of file core_cm55.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 381 of file core_cm55.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 407 of file core_cm55.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 408 of file core_cm55.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 410 of file core_cm55.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 411 of file core_cm55.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 413 of file core_cm55.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 414 of file core_cm55.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 416 of file core_cm55.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 417 of file core_cm55.h.
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
Definition at line 419 of file core_cm55.h.
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
Definition at line 420 of file core_cm55.h.
| #define xPSR_IT_Pos 25U |
xPSR: IT Position
Definition at line 422 of file core_cm55.h.
| #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) |
xPSR: IT Mask
Definition at line 423 of file core_cm55.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 425 of file core_cm55.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 426 of file core_cm55.h.
| #define xPSR_GE_Pos 16U |
xPSR: GE Position
Definition at line 428 of file core_cm55.h.
| #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) |
xPSR: GE Mask
Definition at line 429 of file core_cm55.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 431 of file core_cm55.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 432 of file core_cm55.h.
| #define CONTROL_SFPA_Pos 3U |
CONTROL: SFPA Position
Definition at line 452 of file core_cm55.h.
| #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) |
CONTROL: SFPA Mask
Definition at line 453 of file core_cm55.h.
| #define CONTROL_FPCA_Pos 2U |
CONTROL: FPCA Position
Definition at line 455 of file core_cm55.h.
| #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) |
CONTROL: FPCA Mask
Definition at line 456 of file core_cm55.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 458 of file core_cm55.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 459 of file core_cm55.h.
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
Definition at line 461 of file core_cm55.h.
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
Definition at line 462 of file core_cm55.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 296 of file core_cm7.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 297 of file core_cm7.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 299 of file core_cm7.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 300 of file core_cm7.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 302 of file core_cm7.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 303 of file core_cm7.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 305 of file core_cm7.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 306 of file core_cm7.h.
| #define APSR_Q_Pos 27U |
APSR: Q Position
Definition at line 308 of file core_cm7.h.
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
Definition at line 309 of file core_cm7.h.
| #define APSR_GE_Pos 16U |
APSR: GE Position
Definition at line 311 of file core_cm7.h.
| #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) |
APSR: GE Mask
Definition at line 312 of file core_cm7.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 329 of file core_cm7.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 330 of file core_cm7.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 357 of file core_cm7.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 358 of file core_cm7.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 360 of file core_cm7.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 361 of file core_cm7.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 363 of file core_cm7.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 364 of file core_cm7.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 366 of file core_cm7.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 367 of file core_cm7.h.
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
Definition at line 369 of file core_cm7.h.
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
Definition at line 370 of file core_cm7.h.
| #define xPSR_ICI_IT_2_Pos 25U |
xPSR: ICI/IT part 2 Position
Definition at line 372 of file core_cm7.h.
| #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) |
xPSR: ICI/IT part 2 Mask
Definition at line 373 of file core_cm7.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 375 of file core_cm7.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 376 of file core_cm7.h.
| #define xPSR_GE_Pos 16U |
xPSR: GE Position
Definition at line 378 of file core_cm7.h.
| #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) |
xPSR: GE Mask
Definition at line 379 of file core_cm7.h.
| #define xPSR_ICI_IT_1_Pos 10U |
xPSR: ICI/IT part 1 Position
Definition at line 381 of file core_cm7.h.
| #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) |
xPSR: ICI/IT part 1 Mask
Definition at line 382 of file core_cm7.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 384 of file core_cm7.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 385 of file core_cm7.h.
| #define CONTROL_FPCA_Pos 2U |
CONTROL: FPCA Position
Definition at line 404 of file core_cm7.h.
| #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) |
CONTROL: FPCA Mask
Definition at line 405 of file core_cm7.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 407 of file core_cm7.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 408 of file core_cm7.h.
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
Definition at line 410 of file core_cm7.h.
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
Definition at line 411 of file core_cm7.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 343 of file core_cm85.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 344 of file core_cm85.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 346 of file core_cm85.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 347 of file core_cm85.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 349 of file core_cm85.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 350 of file core_cm85.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 352 of file core_cm85.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 353 of file core_cm85.h.
| #define APSR_Q_Pos 27U |
APSR: Q Position
Definition at line 355 of file core_cm85.h.
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
Definition at line 356 of file core_cm85.h.
| #define APSR_GE_Pos 16U |
APSR: GE Position
Definition at line 358 of file core_cm85.h.
| #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) |
APSR: GE Mask
Definition at line 359 of file core_cm85.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 376 of file core_cm85.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 377 of file core_cm85.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 405 of file core_cm85.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 406 of file core_cm85.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 408 of file core_cm85.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 409 of file core_cm85.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 411 of file core_cm85.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 412 of file core_cm85.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 414 of file core_cm85.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 415 of file core_cm85.h.
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
Definition at line 417 of file core_cm85.h.
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
Definition at line 418 of file core_cm85.h.
| #define xPSR_IT_Pos 25U |
xPSR: IT Position
Definition at line 420 of file core_cm85.h.
| #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) |
xPSR: IT Mask
Definition at line 421 of file core_cm85.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 423 of file core_cm85.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 424 of file core_cm85.h.
| #define xPSR_B_Pos 21U |
xPSR: B Position
Definition at line 426 of file core_cm85.h.
| #define xPSR_B_Msk (1UL << xPSR_B_Pos) |
xPSR: B Mask
Definition at line 427 of file core_cm85.h.
| #define xPSR_GE_Pos 16U |
xPSR: GE Position
Definition at line 429 of file core_cm85.h.
| #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) |
xPSR: GE Mask
Definition at line 430 of file core_cm85.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 432 of file core_cm85.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 433 of file core_cm85.h.
| #define CONTROL_UPAC_EN_Pos 7U |
CONTROL: UPAC_EN Position
Definition at line 457 of file core_cm85.h.
| #define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) |
CONTROL: UPAC_EN Mask
Definition at line 458 of file core_cm85.h.
| #define CONTROL_PAC_EN_Pos 6U |
CONTROL: PAC_EN Position
Definition at line 460 of file core_cm85.h.
| #define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) |
CONTROL: PAC_EN Mask
Definition at line 461 of file core_cm85.h.
| #define CONTROL_UBTI_EN_Pos 5U |
CONTROL: UBTI_EN Position
Definition at line 463 of file core_cm85.h.
| #define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) |
CONTROL: UBTI_EN Mask
Definition at line 464 of file core_cm85.h.
| #define CONTROL_BTI_EN_Pos 4U |
CONTROL: BTI_EN Position
Definition at line 466 of file core_cm85.h.
| #define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) |
CONTROL: BTI_EN Mask
Definition at line 467 of file core_cm85.h.
| #define CONTROL_SFPA_Pos 3U |
CONTROL: SFPA Position
Definition at line 469 of file core_cm85.h.
| #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) |
CONTROL: SFPA Mask
Definition at line 470 of file core_cm85.h.
| #define CONTROL_FPCA_Pos 2U |
CONTROL: FPCA Position
Definition at line 472 of file core_cm85.h.
| #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) |
CONTROL: FPCA Mask
Definition at line 473 of file core_cm85.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 475 of file core_cm85.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 476 of file core_cm85.h.
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
Definition at line 478 of file core_cm85.h.
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
Definition at line 479 of file core_cm85.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 224 of file core_sc000.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 225 of file core_sc000.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 227 of file core_sc000.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 228 of file core_sc000.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 230 of file core_sc000.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 231 of file core_sc000.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 233 of file core_sc000.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 234 of file core_sc000.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 251 of file core_sc000.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 252 of file core_sc000.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 275 of file core_sc000.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 276 of file core_sc000.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 278 of file core_sc000.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 279 of file core_sc000.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 281 of file core_sc000.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 282 of file core_sc000.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 284 of file core_sc000.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 285 of file core_sc000.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 287 of file core_sc000.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 288 of file core_sc000.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 290 of file core_sc000.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 291 of file core_sc000.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 309 of file core_sc000.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 310 of file core_sc000.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 226 of file core_sc300.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 227 of file core_sc300.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 229 of file core_sc300.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 230 of file core_sc300.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 232 of file core_sc300.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 233 of file core_sc300.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 235 of file core_sc300.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 236 of file core_sc300.h.
| #define APSR_Q_Pos 27U |
APSR: Q Position
Definition at line 238 of file core_sc300.h.
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
Definition at line 239 of file core_sc300.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 256 of file core_sc300.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 257 of file core_sc300.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 283 of file core_sc300.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 284 of file core_sc300.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 286 of file core_sc300.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 287 of file core_sc300.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 289 of file core_sc300.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 290 of file core_sc300.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 292 of file core_sc300.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 293 of file core_sc300.h.
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
Definition at line 295 of file core_sc300.h.
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
Definition at line 296 of file core_sc300.h.
| #define xPSR_ICI_IT_2_Pos 25U |
xPSR: ICI/IT part 2 Position
Definition at line 298 of file core_sc300.h.
| #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) |
xPSR: ICI/IT part 2 Mask
Definition at line 299 of file core_sc300.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 301 of file core_sc300.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 302 of file core_sc300.h.
| #define xPSR_ICI_IT_1_Pos 10U |
xPSR: ICI/IT part 1 Position
Definition at line 304 of file core_sc300.h.
| #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) |
xPSR: ICI/IT part 1 Mask
Definition at line 305 of file core_sc300.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 307 of file core_sc300.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 308 of file core_sc300.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 326 of file core_sc300.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 327 of file core_sc300.h.
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
Definition at line 329 of file core_sc300.h.
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
Definition at line 330 of file core_sc300.h.
| #define APSR_N_Pos 31U |
APSR: N Position
Definition at line 344 of file core_starmc1.h.
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
Definition at line 345 of file core_starmc1.h.
| #define APSR_Z_Pos 30U |
APSR: Z Position
Definition at line 347 of file core_starmc1.h.
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
Definition at line 348 of file core_starmc1.h.
| #define APSR_C_Pos 29U |
APSR: C Position
Definition at line 350 of file core_starmc1.h.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
Definition at line 351 of file core_starmc1.h.
| #define APSR_V_Pos 28U |
APSR: V Position
Definition at line 353 of file core_starmc1.h.
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
Definition at line 354 of file core_starmc1.h.
| #define APSR_Q_Pos 27U |
APSR: Q Position
Definition at line 356 of file core_starmc1.h.
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
Definition at line 357 of file core_starmc1.h.
| #define APSR_GE_Pos 16U |
APSR: GE Position
Definition at line 359 of file core_starmc1.h.
| #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) |
APSR: GE Mask
Definition at line 360 of file core_starmc1.h.
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
Definition at line 377 of file core_starmc1.h.
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
Definition at line 378 of file core_starmc1.h.
| #define xPSR_N_Pos 31U |
xPSR: N Position
Definition at line 404 of file core_starmc1.h.
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
Definition at line 405 of file core_starmc1.h.
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
Definition at line 407 of file core_starmc1.h.
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
Definition at line 408 of file core_starmc1.h.
| #define xPSR_C_Pos 29U |
xPSR: C Position
Definition at line 410 of file core_starmc1.h.
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
Definition at line 411 of file core_starmc1.h.
| #define xPSR_V_Pos 28U |
xPSR: V Position
Definition at line 413 of file core_starmc1.h.
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
Definition at line 414 of file core_starmc1.h.
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
Definition at line 416 of file core_starmc1.h.
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
Definition at line 417 of file core_starmc1.h.
| #define xPSR_IT_Pos 25U |
xPSR: IT Position
Definition at line 419 of file core_starmc1.h.
| #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) |
xPSR: IT Mask
Definition at line 420 of file core_starmc1.h.
| #define xPSR_T_Pos 24U |
xPSR: T Position
Definition at line 422 of file core_starmc1.h.
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
Definition at line 423 of file core_starmc1.h.
| #define xPSR_GE_Pos 16U |
xPSR: GE Position
Definition at line 425 of file core_starmc1.h.
| #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) |
xPSR: GE Mask
Definition at line 426 of file core_starmc1.h.
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
Definition at line 428 of file core_starmc1.h.
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
Definition at line 429 of file core_starmc1.h.
| #define CONTROL_SFPA_Pos 3U |
CONTROL: SFPA Position
Definition at line 449 of file core_starmc1.h.
| #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) |
CONTROL: SFPA Mask
Definition at line 450 of file core_starmc1.h.
| #define CONTROL_FPCA_Pos 2U |
CONTROL: FPCA Position
Definition at line 452 of file core_starmc1.h.
| #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) |
CONTROL: FPCA Mask
Definition at line 453 of file core_starmc1.h.
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
Definition at line 455 of file core_starmc1.h.
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
Definition at line 456 of file core_starmc1.h.
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
Definition at line 458 of file core_starmc1.h.
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
Definition at line 459 of file core_starmc1.h.
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
Definition at line 495 of file core_armv81mml.h.
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
Definition at line 496 of file core_armv81mml.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 563 of file core_armv81mml.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 564 of file core_armv81mml.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 566 of file core_armv81mml.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 567 of file core_armv81mml.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 569 of file core_armv81mml.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 570 of file core_armv81mml.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 572 of file core_armv81mml.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 573 of file core_armv81mml.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 575 of file core_armv81mml.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 576 of file core_armv81mml.h.
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
Definition at line 579 of file core_armv81mml.h.
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
Definition at line 580 of file core_armv81mml.h.
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
Definition at line 582 of file core_armv81mml.h.
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
Definition at line 583 of file core_armv81mml.h.
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
Definition at line 585 of file core_armv81mml.h.
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
Definition at line 586 of file core_armv81mml.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 588 of file core_armv81mml.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 589 of file core_armv81mml.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 591 of file core_armv81mml.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 592 of file core_armv81mml.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 594 of file core_armv81mml.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 595 of file core_armv81mml.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 597 of file core_armv81mml.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 598 of file core_armv81mml.h.
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
Definition at line 600 of file core_armv81mml.h.
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
Definition at line 601 of file core_armv81mml.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 603 of file core_armv81mml.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 604 of file core_armv81mml.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 606 of file core_armv81mml.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 607 of file core_armv81mml.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 609 of file core_armv81mml.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 610 of file core_armv81mml.h.
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
Definition at line 612 of file core_armv81mml.h.
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
Definition at line 613 of file core_armv81mml.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 615 of file core_armv81mml.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 616 of file core_armv81mml.h.
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
Definition at line 619 of file core_armv81mml.h.
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
Definition at line 620 of file core_armv81mml.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 623 of file core_armv81mml.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 624 of file core_armv81mml.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 626 of file core_armv81mml.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 627 of file core_armv81mml.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 629 of file core_armv81mml.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 630 of file core_armv81mml.h.
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
Definition at line 632 of file core_armv81mml.h.
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
Definition at line 633 of file core_armv81mml.h.
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
Definition at line 635 of file core_armv81mml.h.
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
Definition at line 636 of file core_armv81mml.h.
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
Definition at line 638 of file core_armv81mml.h.
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
Definition at line 639 of file core_armv81mml.h.
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
Definition at line 647 of file core_armv81mml.h.
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
Definition at line 648 of file core_armv81mml.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 650 of file core_armv81mml.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 651 of file core_armv81mml.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 653 of file core_armv81mml.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 654 of file core_armv81mml.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 657 of file core_armv81mml.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 658 of file core_armv81mml.h.
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
Definition at line 660 of file core_armv81mml.h.
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
Definition at line 661 of file core_armv81mml.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 663 of file core_armv81mml.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 664 of file core_armv81mml.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 666 of file core_armv81mml.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 667 of file core_armv81mml.h.
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
SCB CCR: Branch prediction enable bit Position
Definition at line 676 of file core_armv81mml.h.
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
SCB CCR: Branch prediction enable bit Mask
Definition at line 677 of file core_armv81mml.h.
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
SCB CCR: Instruction cache enable bit Position
Definition at line 679 of file core_armv81mml.h.
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
SCB CCR: Instruction cache enable bit Mask
Definition at line 680 of file core_armv81mml.h.
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
SCB CCR: Cache enable bit Position
Definition at line 682 of file core_armv81mml.h.
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
Definition at line 685 of file core_armv81mml.h.
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
Definition at line 686 of file core_armv81mml.h.
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
Definition at line 688 of file core_armv81mml.h.
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
Definition at line 689 of file core_armv81mml.h.
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
Definition at line 691 of file core_armv81mml.h.
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
Definition at line 692 of file core_armv81mml.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 694 of file core_armv81mml.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 695 of file core_armv81mml.h.
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
Definition at line 697 of file core_armv81mml.h.
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
Definition at line 698 of file core_armv81mml.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
Definition at line 701 of file core_armv81mml.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
Definition at line 702 of file core_armv81mml.h.
| #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
SCB SHCSR: SECUREFAULTPENDED Position
Definition at line 704 of file core_armv81mml.h.
| #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
SCB SHCSR: SECUREFAULTPENDED Mask
Definition at line 705 of file core_armv81mml.h.
| #define SCB_SHCSR_SECUREFAULTENA_Pos 19U |
SCB SHCSR: SECUREFAULTENA Position
Definition at line 707 of file core_armv81mml.h.
| #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
SCB SHCSR: SECUREFAULTENA Mask
Definition at line 708 of file core_armv81mml.h.
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
Definition at line 710 of file core_armv81mml.h.
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
Definition at line 711 of file core_armv81mml.h.
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
Definition at line 713 of file core_armv81mml.h.
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
Definition at line 714 of file core_armv81mml.h.
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
Definition at line 716 of file core_armv81mml.h.
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
Definition at line 717 of file core_armv81mml.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 719 of file core_armv81mml.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 720 of file core_armv81mml.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
Definition at line 722 of file core_armv81mml.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
Definition at line 723 of file core_armv81mml.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
Definition at line 725 of file core_armv81mml.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
Definition at line 726 of file core_armv81mml.h.
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
Definition at line 728 of file core_armv81mml.h.
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
Definition at line 729 of file core_armv81mml.h.
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
Definition at line 731 of file core_armv81mml.h.
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
Definition at line 732 of file core_armv81mml.h.
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
Definition at line 734 of file core_armv81mml.h.
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
Definition at line 735 of file core_armv81mml.h.
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
Definition at line 737 of file core_armv81mml.h.
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
Definition at line 738 of file core_armv81mml.h.
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
Definition at line 740 of file core_armv81mml.h.
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
Definition at line 741 of file core_armv81mml.h.
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
Definition at line 743 of file core_armv81mml.h.
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
Definition at line 744 of file core_armv81mml.h.
| #define SCB_SHCSR_SECUREFAULTACT_Pos 4U |
SCB SHCSR: SECUREFAULTACT Position
Definition at line 746 of file core_armv81mml.h.
| #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
SCB SHCSR: SECUREFAULTACT Mask
Definition at line 747 of file core_armv81mml.h.
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
Definition at line 749 of file core_armv81mml.h.
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
Definition at line 750 of file core_armv81mml.h.
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
Definition at line 752 of file core_armv81mml.h.
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
Definition at line 753 of file core_armv81mml.h.
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
Definition at line 755 of file core_armv81mml.h.
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
Definition at line 756 of file core_armv81mml.h.
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
Definition at line 758 of file core_armv81mml.h.
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
Definition at line 759 of file core_armv81mml.h.
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
Definition at line 762 of file core_armv81mml.h.
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
Definition at line 763 of file core_armv81mml.h.
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
Definition at line 765 of file core_armv81mml.h.
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
Definition at line 766 of file core_armv81mml.h.
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
Definition at line 768 of file core_armv81mml.h.
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
Definition at line 769 of file core_armv81mml.h.
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
Definition at line 772 of file core_armv81mml.h.
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
Definition at line 773 of file core_armv81mml.h.
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
Definition at line 775 of file core_armv81mml.h.
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
Definition at line 776 of file core_armv81mml.h.
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
Definition at line 778 of file core_armv81mml.h.
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
Definition at line 779 of file core_armv81mml.h.
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
Definition at line 781 of file core_armv81mml.h.
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
Definition at line 782 of file core_armv81mml.h.
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
Definition at line 784 of file core_armv81mml.h.
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
Definition at line 785 of file core_armv81mml.h.
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
Definition at line 787 of file core_armv81mml.h.
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
Definition at line 788 of file core_armv81mml.h.
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
Definition at line 791 of file core_armv81mml.h.
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
Definition at line 792 of file core_armv81mml.h.
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
Definition at line 794 of file core_armv81mml.h.
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
Definition at line 795 of file core_armv81mml.h.
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
Definition at line 797 of file core_armv81mml.h.
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
Definition at line 798 of file core_armv81mml.h.
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
Definition at line 800 of file core_armv81mml.h.
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
Definition at line 801 of file core_armv81mml.h.
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
Definition at line 803 of file core_armv81mml.h.
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
Definition at line 804 of file core_armv81mml.h.
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
Definition at line 806 of file core_armv81mml.h.
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
Definition at line 807 of file core_armv81mml.h.
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
Definition at line 809 of file core_armv81mml.h.
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
Definition at line 810 of file core_armv81mml.h.
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
Definition at line 813 of file core_armv81mml.h.
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
Definition at line 814 of file core_armv81mml.h.
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
Definition at line 816 of file core_armv81mml.h.
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
Definition at line 817 of file core_armv81mml.h.
| #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
SCB CFSR (UFSR): STKOF Position
Definition at line 819 of file core_armv81mml.h.
| #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
SCB CFSR (UFSR): STKOF Mask
Definition at line 820 of file core_armv81mml.h.
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
Definition at line 822 of file core_armv81mml.h.
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
Definition at line 823 of file core_armv81mml.h.
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
Definition at line 825 of file core_armv81mml.h.
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
Definition at line 826 of file core_armv81mml.h.
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
Definition at line 828 of file core_armv81mml.h.
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
Definition at line 829 of file core_armv81mml.h.
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
Definition at line 831 of file core_armv81mml.h.
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
Definition at line 832 of file core_armv81mml.h.
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
Definition at line 835 of file core_armv81mml.h.
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
Definition at line 836 of file core_armv81mml.h.
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
Definition at line 838 of file core_armv81mml.h.
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
Definition at line 839 of file core_armv81mml.h.
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
Definition at line 841 of file core_armv81mml.h.
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
Definition at line 842 of file core_armv81mml.h.
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
Definition at line 848 of file core_armv81mml.h.
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
Definition at line 849 of file core_armv81mml.h.
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
Definition at line 851 of file core_armv81mml.h.
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
Definition at line 852 of file core_armv81mml.h.
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
Definition at line 854 of file core_armv81mml.h.
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
Definition at line 855 of file core_armv81mml.h.
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
Definition at line 857 of file core_armv81mml.h.
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
Definition at line 858 of file core_armv81mml.h.
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
Definition at line 860 of file core_armv81mml.h.
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
Definition at line 861 of file core_armv81mml.h.
| #define SCB_NSACR_CP11_Pos 11U |
SCB NSACR: CP11 Position
Definition at line 864 of file core_armv81mml.h.
| #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
SCB NSACR: CP11 Mask
Definition at line 865 of file core_armv81mml.h.
| #define SCB_NSACR_CP10_Pos 10U |
SCB NSACR: CP10 Position
Definition at line 867 of file core_armv81mml.h.
| #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
SCB NSACR: CP10 Mask
Definition at line 868 of file core_armv81mml.h.
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
Definition at line 902 of file core_armv81mml.h.
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
Definition at line 903 of file core_armv81mml.h.
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
Definition at line 905 of file core_armv81mml.h.
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
Definition at line 906 of file core_armv81mml.h.
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
Definition at line 909 of file core_armv81mml.h.
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
Definition at line 910 of file core_armv81mml.h.
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
Definition at line 912 of file core_armv81mml.h.
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
Definition at line 913 of file core_armv81mml.h.
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
Definition at line 915 of file core_armv81mml.h.
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
Definition at line 916 of file core_armv81mml.h.
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
Definition at line 918 of file core_armv81mml.h.
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
Definition at line 919 of file core_armv81mml.h.
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
Definition at line 921 of file core_armv81mml.h.
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
Definition at line 922 of file core_armv81mml.h.
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
Definition at line 925 of file core_armv81mml.h.
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
Definition at line 926 of file core_armv81mml.h.
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
Definition at line 928 of file core_armv81mml.h.
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
Definition at line 929 of file core_armv81mml.h.
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
Definition at line 931 of file core_armv81mml.h.
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
Definition at line 932 of file core_armv81mml.h.
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
Definition at line 934 of file core_armv81mml.h.
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
Definition at line 935 of file core_armv81mml.h.
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
Definition at line 937 of file core_armv81mml.h.
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
Definition at line 938 of file core_armv81mml.h.
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
Definition at line 940 of file core_armv81mml.h.
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
Definition at line 941 of file core_armv81mml.h.
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
Definition at line 943 of file core_armv81mml.h.
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
Definition at line 944 of file core_armv81mml.h.
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
Definition at line 947 of file core_armv81mml.h.
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
Definition at line 948 of file core_armv81mml.h.
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
Definition at line 950 of file core_armv81mml.h.
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
Definition at line 951 of file core_armv81mml.h.
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
Definition at line 954 of file core_armv81mml.h.
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
Definition at line 955 of file core_armv81mml.h.
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
Definition at line 968 of file core_armv81mml.h.
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
Definition at line 969 of file core_armv81mml.h.
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
Definition at line 971 of file core_armv81mml.h.
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
Definition at line 972 of file core_armv81mml.h.
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
Definition at line 975 of file core_armv81mml.h.
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
Definition at line 976 of file core_armv81mml.h.
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
Definition at line 978 of file core_armv81mml.h.
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
Definition at line 979 of file core_armv81mml.h.
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
Definition at line 982 of file core_armv81mml.h.
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
Definition at line 983 of file core_armv81mml.h.
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
Definition at line 985 of file core_armv81mml.h.
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
Definition at line 986 of file core_armv81mml.h.
| #define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
Definition at line 1010 of file core_armv81mml.h.
| #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
Definition at line 1011 of file core_armv81mml.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 1035 of file core_armv81mml.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 1036 of file core_armv81mml.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 1038 of file core_armv81mml.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 1039 of file core_armv81mml.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 1041 of file core_armv81mml.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 1042 of file core_armv81mml.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 1044 of file core_armv81mml.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 1045 of file core_armv81mml.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 1048 of file core_armv81mml.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 1049 of file core_armv81mml.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 1052 of file core_armv81mml.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 1053 of file core_armv81mml.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 1056 of file core_armv81mml.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 1057 of file core_armv81mml.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 1059 of file core_armv81mml.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 1060 of file core_armv81mml.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 1062 of file core_armv81mml.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 1063 of file core_armv81mml.h.
| #define ITM_STIM_DISABLED_Pos 1U |
ITM STIM: DISABLED Position
Definition at line 1115 of file core_armv81mml.h.
| #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) |
ITM STIM: DISABLED Mask
Definition at line 1116 of file core_armv81mml.h.
| #define ITM_STIM_FIFOREADY_Pos 0U |
ITM STIM: FIFOREADY Position
Definition at line 1118 of file core_armv81mml.h.
| #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) |
ITM STIM: FIFOREADY Mask
Definition at line 1119 of file core_armv81mml.h.
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
Definition at line 1122 of file core_armv81mml.h.
| #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
Definition at line 1123 of file core_armv81mml.h.
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
Definition at line 1126 of file core_armv81mml.h.
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
Definition at line 1127 of file core_armv81mml.h.
| #define ITM_TCR_TRACEBUSID_Pos 16U |
ITM TCR: ATBID Position
Definition at line 1129 of file core_armv81mml.h.
| #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) |
ITM TCR: ATBID Mask
Definition at line 1130 of file core_armv81mml.h.
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
Definition at line 1132 of file core_armv81mml.h.
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
Definition at line 1133 of file core_armv81mml.h.
| #define ITM_TCR_TSPRESCALE_Pos 8U |
ITM TCR: TSPRESCALE Position
Definition at line 1135 of file core_armv81mml.h.
| #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) |
ITM TCR: TSPRESCALE Mask
Definition at line 1136 of file core_armv81mml.h.
| #define ITM_TCR_STALLENA_Pos 5U |
ITM TCR: STALLENA Position
Definition at line 1138 of file core_armv81mml.h.
| #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) |
ITM TCR: STALLENA Mask
Definition at line 1139 of file core_armv81mml.h.
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
Definition at line 1141 of file core_armv81mml.h.
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
Definition at line 1142 of file core_armv81mml.h.
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
Definition at line 1144 of file core_armv81mml.h.
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
Definition at line 1145 of file core_armv81mml.h.
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
Definition at line 1147 of file core_armv81mml.h.
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
Definition at line 1148 of file core_armv81mml.h.
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
Definition at line 1150 of file core_armv81mml.h.
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
Definition at line 1151 of file core_armv81mml.h.
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
Definition at line 1153 of file core_armv81mml.h.
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
Definition at line 1154 of file core_armv81mml.h.
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
Definition at line 1157 of file core_armv81mml.h.
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
Definition at line 1158 of file core_armv81mml.h.
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
Definition at line 1160 of file core_armv81mml.h.
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
Definition at line 1161 of file core_armv81mml.h.
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
Definition at line 1163 of file core_armv81mml.h.
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
Definition at line 1164 of file core_armv81mml.h.
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
Definition at line 1259 of file core_armv81mml.h.
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
Definition at line 1260 of file core_armv81mml.h.
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
Definition at line 1262 of file core_armv81mml.h.
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
Definition at line 1263 of file core_armv81mml.h.
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
Definition at line 1265 of file core_armv81mml.h.
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
Definition at line 1266 of file core_armv81mml.h.
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
Definition at line 1268 of file core_armv81mml.h.
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
Definition at line 1269 of file core_armv81mml.h.
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
Definition at line 1271 of file core_armv81mml.h.
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
Definition at line 1272 of file core_armv81mml.h.
| #define DWT_CTRL_CYCDISS_Pos 23U |
DWT CTRL: CYCDISS Position
Definition at line 1274 of file core_armv81mml.h.
| #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) |
DWT CTRL: CYCDISS Mask
Definition at line 1275 of file core_armv81mml.h.
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
Definition at line 1277 of file core_armv81mml.h.
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
Definition at line 1278 of file core_armv81mml.h.
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
Definition at line 1280 of file core_armv81mml.h.
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
Definition at line 1281 of file core_armv81mml.h.
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
Definition at line 1283 of file core_armv81mml.h.
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
Definition at line 1284 of file core_armv81mml.h.
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
Definition at line 1286 of file core_armv81mml.h.
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
Definition at line 1287 of file core_armv81mml.h.
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
Definition at line 1289 of file core_armv81mml.h.
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
Definition at line 1290 of file core_armv81mml.h.
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
Definition at line 1292 of file core_armv81mml.h.
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
Definition at line 1293 of file core_armv81mml.h.
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
Definition at line 1295 of file core_armv81mml.h.
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
Definition at line 1296 of file core_armv81mml.h.
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
Definition at line 1298 of file core_armv81mml.h.
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
Definition at line 1299 of file core_armv81mml.h.
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
Definition at line 1301 of file core_armv81mml.h.
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
Definition at line 1302 of file core_armv81mml.h.
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
Definition at line 1304 of file core_armv81mml.h.
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
Definition at line 1305 of file core_armv81mml.h.
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
Definition at line 1307 of file core_armv81mml.h.
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
Definition at line 1308 of file core_armv81mml.h.
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
Definition at line 1310 of file core_armv81mml.h.
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
Definition at line 1311 of file core_armv81mml.h.
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
Definition at line 1313 of file core_armv81mml.h.
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
Definition at line 1314 of file core_armv81mml.h.
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
Definition at line 1317 of file core_armv81mml.h.
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
Definition at line 1318 of file core_armv81mml.h.
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
Definition at line 1321 of file core_armv81mml.h.
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
Definition at line 1322 of file core_armv81mml.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
Definition at line 1325 of file core_armv81mml.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
Definition at line 1326 of file core_armv81mml.h.
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
Definition at line 1329 of file core_armv81mml.h.
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
Definition at line 1330 of file core_armv81mml.h.
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
Definition at line 1333 of file core_armv81mml.h.
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
Definition at line 1334 of file core_armv81mml.h.
| #define DWT_FUNCTION_ID_Pos 27U |
DWT FUNCTION: ID Position
Definition at line 1337 of file core_armv81mml.h.
| #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) |
DWT FUNCTION: ID Mask
Definition at line 1338 of file core_armv81mml.h.
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
Definition at line 1340 of file core_armv81mml.h.
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
Definition at line 1341 of file core_armv81mml.h.
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
Definition at line 1343 of file core_armv81mml.h.
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
Definition at line 1344 of file core_armv81mml.h.
| #define DWT_FUNCTION_ACTION_Pos 4U |
DWT FUNCTION: ACTION Position
Definition at line 1346 of file core_armv81mml.h.
| #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) |
DWT FUNCTION: ACTION Mask
Definition at line 1347 of file core_armv81mml.h.
| #define DWT_FUNCTION_MATCH_Pos 0U |
DWT FUNCTION: MATCH Position
Definition at line 1349 of file core_armv81mml.h.
| #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) |
DWT FUNCTION: MATCH Mask
Definition at line 1350 of file core_armv81mml.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 1390 of file core_armv81mml.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 1391 of file core_armv81mml.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 1394 of file core_armv81mml.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 1395 of file core_armv81mml.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 1397 of file core_armv81mml.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 1398 of file core_armv81mml.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 1400 of file core_armv81mml.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 1401 of file core_armv81mml.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 1403 of file core_armv81mml.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 1404 of file core_armv81mml.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 1407 of file core_armv81mml.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 1408 of file core_armv81mml.h.
| #define TPI_FFCR_FOnMan_Pos 6U |
TPI FFCR: FOnMan Position
Definition at line 1410 of file core_armv81mml.h.
| #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) |
TPI FFCR: FOnMan Mask
Definition at line 1411 of file core_armv81mml.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 1431 of file core_armv81mml.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1432 of file core_armv81mml.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 1434 of file core_armv81mml.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1435 of file core_armv81mml.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 1437 of file core_armv81mml.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1438 of file core_armv81mml.h.
| #define TPI_DEVID_FIFOSZ_Pos 6U |
TPI DEVID: FIFO depth Position
TPI DEVID: FIFOSZ Position
Definition at line 1440 of file core_armv81mml.h.
| #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) |
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
Definition at line 1444 of file core_armv81mml.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 1445 of file core_armv81mml.h.
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
Definition at line 1447 of file core_armv81mml.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1448 of file core_armv81mml.h.
| #define MPU_TYPE_IREGION_Pos 16U |
MPU TYPE: IREGION Position
Definition at line 2306 of file core_armv81mml.h.
| #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) |
MPU TYPE: IREGION Mask
Definition at line 2307 of file core_armv81mml.h.
| #define MPU_TYPE_DREGION_Pos 8U |
MPU TYPE: DREGION Position
Definition at line 2309 of file core_armv81mml.h.
| #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) |
MPU TYPE: DREGION Mask
Definition at line 2310 of file core_armv81mml.h.
| #define MPU_TYPE_SEPARATE_Pos 0U |
MPU TYPE: SEPARATE Position
Definition at line 2312 of file core_armv81mml.h.
| #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) |
MPU TYPE: SEPARATE Mask
Definition at line 2313 of file core_armv81mml.h.
| #define MPU_CTRL_PRIVDEFENA_Pos 2U |
MPU CTRL: PRIVDEFENA Position
Definition at line 2316 of file core_armv81mml.h.
| #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) |
MPU CTRL: PRIVDEFENA Mask
Definition at line 2317 of file core_armv81mml.h.
| #define MPU_CTRL_HFNMIENA_Pos 1U |
MPU CTRL: HFNMIENA Position
Definition at line 2319 of file core_armv81mml.h.
| #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) |
MPU CTRL: HFNMIENA Mask
Definition at line 2320 of file core_armv81mml.h.
| #define MPU_CTRL_ENABLE_Pos 0U |
MPU CTRL: ENABLE Position
Definition at line 2322 of file core_armv81mml.h.
| #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) |
MPU CTRL: ENABLE Mask
Definition at line 2323 of file core_armv81mml.h.
| #define MPU_RNR_REGION_Pos 0U |
MPU RNR: REGION Position
Definition at line 2326 of file core_armv81mml.h.
| #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) |
MPU RNR: REGION Mask
Definition at line 2327 of file core_armv81mml.h.
| #define MPU_RBAR_BASE_Pos 5U |
MPU RBAR: BASE Position
Definition at line 2330 of file core_armv81mml.h.
| #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) |
MPU RBAR: BASE Mask
Definition at line 2331 of file core_armv81mml.h.
| #define MPU_RBAR_SH_Pos 3U |
MPU RBAR: SH Position
Definition at line 2333 of file core_armv81mml.h.
| #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) |
MPU RBAR: SH Mask
Definition at line 2334 of file core_armv81mml.h.
| #define MPU_RBAR_AP_Pos 1U |
MPU RBAR: AP Position
Definition at line 2336 of file core_armv81mml.h.
| #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) |
MPU RBAR: AP Mask
Definition at line 2337 of file core_armv81mml.h.
| #define MPU_RBAR_XN_Pos 0U |
MPU RBAR: XN Position
Definition at line 2339 of file core_armv81mml.h.
| #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) |
MPU RBAR: XN Mask
Definition at line 2340 of file core_armv81mml.h.
| #define MPU_RLAR_LIMIT_Pos 5U |
MPU RLAR: LIMIT Position
Definition at line 2343 of file core_armv81mml.h.
| #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) |
MPU RLAR: LIMIT Mask
Definition at line 2344 of file core_armv81mml.h.
| #define MPU_RLAR_AttrIndx_Pos 1U |
MPU RLAR: AttrIndx Position
Definition at line 2349 of file core_armv81mml.h.
| #define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) |
MPU RLAR: AttrIndx Mask
Definition at line 2350 of file core_armv81mml.h.
| #define MPU_RLAR_EN_Pos 0U |
MPU RLAR: Region enable bit Position
MPU RLAR: EN Position
Definition at line 2352 of file core_armv81mml.h.
| #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) |
MPU RLAR: Region enable bit Disable Mask
MPU RLAR: EN Mask
Definition at line 2353 of file core_armv81mml.h.
| #define MPU_MAIR0_Attr3_Pos 24U |
MPU MAIR0: Attr3 Position
Definition at line 2356 of file core_armv81mml.h.
| #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) |
MPU MAIR0: Attr3 Mask
Definition at line 2357 of file core_armv81mml.h.
| #define MPU_MAIR0_Attr2_Pos 16U |
MPU MAIR0: Attr2 Position
Definition at line 2359 of file core_armv81mml.h.
| #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) |
MPU MAIR0: Attr2 Mask
Definition at line 2360 of file core_armv81mml.h.
| #define MPU_MAIR0_Attr1_Pos 8U |
MPU MAIR0: Attr1 Position
Definition at line 2362 of file core_armv81mml.h.
| #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) |
MPU MAIR0: Attr1 Mask
Definition at line 2363 of file core_armv81mml.h.
| #define MPU_MAIR0_Attr0_Pos 0U |
MPU MAIR0: Attr0 Position
Definition at line 2365 of file core_armv81mml.h.
| #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) |
MPU MAIR0: Attr0 Mask
Definition at line 2366 of file core_armv81mml.h.
| #define MPU_MAIR1_Attr7_Pos 24U |
MPU MAIR1: Attr7 Position
Definition at line 2369 of file core_armv81mml.h.
| #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) |
MPU MAIR1: Attr7 Mask
Definition at line 2370 of file core_armv81mml.h.
| #define MPU_MAIR1_Attr6_Pos 16U |
MPU MAIR1: Attr6 Position
Definition at line 2372 of file core_armv81mml.h.
| #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) |
MPU MAIR1: Attr6 Mask
Definition at line 2373 of file core_armv81mml.h.
| #define MPU_MAIR1_Attr5_Pos 8U |
MPU MAIR1: Attr5 Position
Definition at line 2375 of file core_armv81mml.h.
| #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) |
MPU MAIR1: Attr5 Mask
Definition at line 2376 of file core_armv81mml.h.
| #define MPU_MAIR1_Attr4_Pos 0U |
MPU MAIR1: Attr4 Position
Definition at line 2378 of file core_armv81mml.h.
| #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) |
MPU MAIR1: Attr4 Mask
Definition at line 2379 of file core_armv81mml.h.
| #define FPU_FPCCR_ASPEN_Pos 31U |
FPCCR: ASPEN bit Position
Definition at line 2494 of file core_armv81mml.h.
| #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) |
FPCCR: ASPEN bit Mask
Definition at line 2495 of file core_armv81mml.h.
| #define FPU_FPCCR_LSPEN_Pos 30U |
FPCCR: LSPEN Position
Definition at line 2497 of file core_armv81mml.h.
| #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) |
FPCCR: LSPEN bit Mask
Definition at line 2498 of file core_armv81mml.h.
| #define FPU_FPCCR_LSPENS_Pos 29U |
FPCCR: LSPENS Position
Definition at line 2500 of file core_armv81mml.h.
| #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) |
FPCCR: LSPENS bit Mask
Definition at line 2501 of file core_armv81mml.h.
| #define FPU_FPCCR_CLRONRET_Pos 28U |
FPCCR: CLRONRET Position
Definition at line 2503 of file core_armv81mml.h.
| #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) |
FPCCR: CLRONRET bit Mask
Definition at line 2504 of file core_armv81mml.h.
| #define FPU_FPCCR_CLRONRETS_Pos 27U |
FPCCR: CLRONRETS Position
Definition at line 2506 of file core_armv81mml.h.
| #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) |
FPCCR: CLRONRETS bit Mask
Definition at line 2507 of file core_armv81mml.h.
| #define FPU_FPCCR_TS_Pos 26U |
FPCCR: TS Position
Definition at line 2509 of file core_armv81mml.h.
| #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) |
FPCCR: TS bit Mask
Definition at line 2510 of file core_armv81mml.h.
| #define FPU_FPCCR_UFRDY_Pos 10U |
FPCCR: UFRDY Position
Definition at line 2512 of file core_armv81mml.h.
| #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) |
FPCCR: UFRDY bit Mask
Definition at line 2513 of file core_armv81mml.h.
| #define FPU_FPCCR_SPLIMVIOL_Pos 9U |
FPCCR: SPLIMVIOL Position
Definition at line 2515 of file core_armv81mml.h.
| #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) |
FPCCR: SPLIMVIOL bit Mask
Definition at line 2516 of file core_armv81mml.h.
| #define FPU_FPCCR_MONRDY_Pos 8U |
FPCCR: MONRDY Position
Definition at line 2518 of file core_armv81mml.h.
| #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) |
FPCCR: MONRDY bit Mask
Definition at line 2519 of file core_armv81mml.h.
| #define FPU_FPCCR_SFRDY_Pos 7U |
FPCCR: SFRDY Position
Definition at line 2521 of file core_armv81mml.h.
| #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) |
FPCCR: SFRDY bit Mask
Definition at line 2522 of file core_armv81mml.h.
| #define FPU_FPCCR_BFRDY_Pos 6U |
FPCCR: BFRDY Position
Definition at line 2524 of file core_armv81mml.h.
| #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) |
FPCCR: BFRDY bit Mask
Definition at line 2525 of file core_armv81mml.h.
| #define FPU_FPCCR_MMRDY_Pos 5U |
FPCCR: MMRDY Position
Definition at line 2527 of file core_armv81mml.h.
| #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) |
FPCCR: MMRDY bit Mask
Definition at line 2528 of file core_armv81mml.h.
| #define FPU_FPCCR_HFRDY_Pos 4U |
FPCCR: HFRDY Position
Definition at line 2530 of file core_armv81mml.h.
| #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) |
FPCCR: HFRDY bit Mask
Definition at line 2531 of file core_armv81mml.h.
| #define FPU_FPCCR_THREAD_Pos 3U |
FPCCR: processor mode bit Position
Definition at line 2533 of file core_armv81mml.h.
| #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) |
FPCCR: processor mode active bit Mask
Definition at line 2534 of file core_armv81mml.h.
| #define FPU_FPCCR_S_Pos 2U |
FPCCR: Security status of the FP context bit Position
Definition at line 2536 of file core_armv81mml.h.
| #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) |
FPCCR: Security status of the FP context bit Mask
Definition at line 2537 of file core_armv81mml.h.
| #define FPU_FPCCR_USER_Pos 1U |
FPCCR: privilege level bit Position
Definition at line 2539 of file core_armv81mml.h.
| #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) |
FPCCR: privilege level bit Mask
Definition at line 2540 of file core_armv81mml.h.
| #define FPU_FPCCR_LSPACT_Pos 0U |
FPCCR: Lazy state preservation active bit Position
Definition at line 2542 of file core_armv81mml.h.
| #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) |
FPCCR: Lazy state preservation active bit Mask
Definition at line 2543 of file core_armv81mml.h.
| #define FPU_FPCAR_ADDRESS_Pos 3U |
FPCAR: ADDRESS bit Position
Definition at line 2546 of file core_armv81mml.h.
| #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) |
FPCAR: ADDRESS bit Mask
Definition at line 2547 of file core_armv81mml.h.
| #define FPU_FPDSCR_AHP_Pos 26U |
FPDSCR: AHP bit Position
Definition at line 2550 of file core_armv81mml.h.
| #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) |
FPDSCR: AHP bit Mask
Definition at line 2551 of file core_armv81mml.h.
| #define FPU_FPDSCR_DN_Pos 25U |
FPDSCR: DN bit Position
Definition at line 2553 of file core_armv81mml.h.
| #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) |
FPDSCR: DN bit Mask
Definition at line 2554 of file core_armv81mml.h.
| #define FPU_FPDSCR_FZ_Pos 24U |
FPDSCR: FZ bit Position
Definition at line 2556 of file core_armv81mml.h.
| #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) |
FPDSCR: FZ bit Mask
Definition at line 2557 of file core_armv81mml.h.
| #define FPU_FPDSCR_RMode_Pos 22U |
FPDSCR: RMode bit Position
Definition at line 2559 of file core_armv81mml.h.
| #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) |
FPDSCR: RMode bit Mask
Definition at line 2560 of file core_armv81mml.h.
| #define FPU_MVFR2_FPMisc_Pos 4U |
MVFR2: FPMisc bits Position
Definition at line 2607 of file core_armv81mml.h.
| #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) |
MVFR2: FPMisc bits Mask
Definition at line 2608 of file core_armv81mml.h.
| #define DCB_DHCSR_DBGKEY_Pos 16U |
DCB DHCSR: Debug key Position
Definition at line 2806 of file core_armv81mml.h.
| #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) |
DCB DHCSR: Debug key Mask
Definition at line 2807 of file core_armv81mml.h.
| #define DCB_DHCSR_S_RESTART_ST_Pos 26U |
DCB DHCSR: Restart sticky status Position
Definition at line 2809 of file core_armv81mml.h.
| #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) |
DCB DHCSR: Restart sticky status Mask
Definition at line 2810 of file core_armv81mml.h.
| #define DCB_DHCSR_S_RESET_ST_Pos 25U |
DCB DHCSR: Reset sticky status Position
Definition at line 2812 of file core_armv81mml.h.
| #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) |
DCB DHCSR: Reset sticky status Mask
Definition at line 2813 of file core_armv81mml.h.
| #define DCB_DHCSR_S_RETIRE_ST_Pos 24U |
DCB DHCSR: Retire sticky status Position
Definition at line 2815 of file core_armv81mml.h.
| #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) |
DCB DHCSR: Retire sticky status Mask
Definition at line 2816 of file core_armv81mml.h.
| #define DCB_DHCSR_S_SDE_Pos 20U |
DCB DHCSR: Secure debug enabled Position
Definition at line 2827 of file core_armv81mml.h.
| #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) |
DCB DHCSR: Secure debug enabled Mask
Definition at line 2828 of file core_armv81mml.h.
| #define DCB_DHCSR_S_LOCKUP_Pos 19U |
DCB DHCSR: Lockup status Position
Definition at line 2830 of file core_armv81mml.h.
| #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) |
DCB DHCSR: Lockup status Mask
Definition at line 2831 of file core_armv81mml.h.
| #define DCB_DHCSR_S_SLEEP_Pos 18U |
DCB DHCSR: Sleeping status Position
Definition at line 2833 of file core_armv81mml.h.
| #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) |
DCB DHCSR: Sleeping status Mask
Definition at line 2834 of file core_armv81mml.h.
| #define DCB_DHCSR_S_HALT_Pos 17U |
DCB DHCSR: Halted status Position
Definition at line 2836 of file core_armv81mml.h.
| #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) |
DCB DHCSR: Halted status Mask
Definition at line 2837 of file core_armv81mml.h.
| #define DCB_DHCSR_S_REGRDY_Pos 16U |
DCB DHCSR: Register ready status Position
Definition at line 2839 of file core_armv81mml.h.
| #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) |
DCB DHCSR: Register ready status Mask
Definition at line 2840 of file core_armv81mml.h.
| #define DCB_DHCSR_C_SNAPSTALL_Pos 5U |
DCB DHCSR: Snap stall control Position
Definition at line 2845 of file core_armv81mml.h.
| #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) |
DCB DHCSR: Snap stall control Mask
Definition at line 2846 of file core_armv81mml.h.
| #define DCB_DHCSR_C_MASKINTS_Pos 3U |
DCB DHCSR: Mask interrupts control Position
Definition at line 2848 of file core_armv81mml.h.
| #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) |
DCB DHCSR: Mask interrupts control Mask
Definition at line 2849 of file core_armv81mml.h.
| #define DCB_DHCSR_C_STEP_Pos 2U |
DCB DHCSR: Step control Position
Definition at line 2851 of file core_armv81mml.h.
| #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) |
DCB DHCSR: Step control Mask
Definition at line 2852 of file core_armv81mml.h.
| #define DCB_DHCSR_C_HALT_Pos 1U |
DCB DHCSR: Halt control Position
Definition at line 2854 of file core_armv81mml.h.
| #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) |
DCB DHCSR: Halt control Mask
Definition at line 2855 of file core_armv81mml.h.
| #define DCB_DHCSR_C_DEBUGEN_Pos 0U |
DCB DHCSR: Debug enable control Position
Definition at line 2857 of file core_armv81mml.h.
| #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) |
DCB DHCSR: Debug enable control Mask
Definition at line 2858 of file core_armv81mml.h.
| #define DCB_DCRSR_REGWnR_Pos 16U |
DCB DCRSR: Register write/not-read Position
Definition at line 2861 of file core_armv81mml.h.
| #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) |
DCB DCRSR: Register write/not-read Mask
Definition at line 2862 of file core_armv81mml.h.
| #define DCB_DCRSR_REGSEL_Pos 0U |
DCB DCRSR: Register selector Position
Definition at line 2864 of file core_armv81mml.h.
| #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) |
DCB DCRSR: Register selector Mask
Definition at line 2865 of file core_armv81mml.h.
| #define DCB_DCRDR_DBGTMP_Pos 0U |
DCB DCRDR: Data temporary buffer Position
Definition at line 2868 of file core_armv81mml.h.
| #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) |
DCB DCRDR: Data temporary buffer Mask
Definition at line 2869 of file core_armv81mml.h.
| #define DCB_DEMCR_TRCENA_Pos 24U |
DCB DEMCR: Trace enable Position
Definition at line 2872 of file core_armv81mml.h.
| #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) |
DCB DEMCR: Trace enable Mask
Definition at line 2873 of file core_armv81mml.h.
| #define DCB_DEMCR_MONPRKEY_Pos 23U |
DCB DEMCR: Monitor pend req key Position
Definition at line 2875 of file core_armv81mml.h.
| #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) |
DCB DEMCR: Monitor pend req key Mask
Definition at line 2876 of file core_armv81mml.h.
| #define DCB_DEMCR_UMON_EN_Pos 21U |
DCB DEMCR: Unprivileged monitor enable Position
Definition at line 2878 of file core_armv81mml.h.
| #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) |
DCB DEMCR: Unprivileged monitor enable Mask
Definition at line 2879 of file core_armv81mml.h.
| #define DCB_DEMCR_SDME_Pos 20U |
DCB DEMCR: Secure DebugMonitor enable Position
Definition at line 2881 of file core_armv81mml.h.
| #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) |
DCB DEMCR: Secure DebugMonitor enable Mask
Definition at line 2882 of file core_armv81mml.h.
| #define DCB_DEMCR_MON_REQ_Pos 19U |
DCB DEMCR: Monitor request Position
Definition at line 2884 of file core_armv81mml.h.
| #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) |
DCB DEMCR: Monitor request Mask
Definition at line 2885 of file core_armv81mml.h.
| #define DCB_DEMCR_MON_STEP_Pos 18U |
DCB DEMCR: Monitor step Position
Definition at line 2887 of file core_armv81mml.h.
| #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) |
DCB DEMCR: Monitor step Mask
Definition at line 2888 of file core_armv81mml.h.
| #define DCB_DEMCR_MON_PEND_Pos 17U |
DCB DEMCR: Monitor pend Position
Definition at line 2890 of file core_armv81mml.h.
| #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) |
DCB DEMCR: Monitor pend Mask
Definition at line 2891 of file core_armv81mml.h.
| #define DCB_DEMCR_MON_EN_Pos 16U |
DCB DEMCR: Monitor enable Position
Definition at line 2893 of file core_armv81mml.h.
| #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) |
DCB DEMCR: Monitor enable Mask
Definition at line 2894 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_SFERR_Pos 11U |
DCB DEMCR: Vector Catch SecureFault Position
Definition at line 2896 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) |
DCB DEMCR: Vector Catch SecureFault Mask
Definition at line 2897 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_HARDERR_Pos 10U |
DCB DEMCR: Vector Catch HardFault errors Position
Definition at line 2899 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) |
DCB DEMCR: Vector Catch HardFault errors Mask
Definition at line 2900 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_INTERR_Pos 9U |
DCB DEMCR: Vector Catch interrupt errors Position
Definition at line 2902 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) |
DCB DEMCR: Vector Catch interrupt errors Mask
Definition at line 2903 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_BUSERR_Pos 8U |
DCB DEMCR: Vector Catch BusFault errors Position
Definition at line 2905 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) |
DCB DEMCR: Vector Catch BusFault errors Mask
Definition at line 2906 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_STATERR_Pos 7U |
DCB DEMCR: Vector Catch state errors Position
Definition at line 2908 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) |
DCB DEMCR: Vector Catch state errors Mask
Definition at line 2909 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_CHKERR_Pos 6U |
DCB DEMCR: Vector Catch check errors Position
Definition at line 2911 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) |
DCB DEMCR: Vector Catch check errors Mask
Definition at line 2912 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_NOCPERR_Pos 5U |
DCB DEMCR: Vector Catch NOCP errors Position
Definition at line 2914 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) |
DCB DEMCR: Vector Catch NOCP errors Mask
Definition at line 2915 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_MMERR_Pos 4U |
DCB DEMCR: Vector Catch MemManage errors Position
Definition at line 2917 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) |
DCB DEMCR: Vector Catch MemManage errors Mask
Definition at line 2918 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_CORERESET_Pos 0U |
DCB DEMCR: Vector Catch Core reset Position
Definition at line 2920 of file core_armv81mml.h.
| #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) |
DCB DEMCR: Vector Catch Core reset Mask
Definition at line 2921 of file core_armv81mml.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position
Definition at line 2946 of file core_armv81mml.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask
Definition at line 2947 of file core_armv81mml.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U |
DCB DAUTHCTRL: Secure non-invasive debug enable select Position
Definition at line 2949 of file core_armv81mml.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) |
DCB DAUTHCTRL: Secure non-invasive debug enable select Mask
Definition at line 2950 of file core_armv81mml.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U |
DCB DAUTHCTRL: Internal Secure invasive debug enable Position
Definition at line 2952 of file core_armv81mml.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure invasive debug enable Mask
Definition at line 2953 of file core_armv81mml.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U |
DCB DAUTHCTRL: Secure invasive debug enable select Position
Definition at line 2955 of file core_armv81mml.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) |
DCB DAUTHCTRL: Secure invasive debug enable select Mask
Definition at line 2956 of file core_armv81mml.h.
| #define DCB_DSCSR_CDSKEY_Pos 17U |
DCB DSCSR: CDS write-enable key Position
Definition at line 2959 of file core_armv81mml.h.
| #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) |
DCB DSCSR: CDS write-enable key Mask
Definition at line 2960 of file core_armv81mml.h.
| #define DCB_DSCSR_CDS_Pos 16U |
DCB DSCSR: Current domain Secure Position
Definition at line 2962 of file core_armv81mml.h.
| #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) |
DCB DSCSR: Current domain Secure Mask
Definition at line 2963 of file core_armv81mml.h.
| #define DCB_DSCSR_SBRSEL_Pos 1U |
DCB DSCSR: Secure banked register select Position
Definition at line 2965 of file core_armv81mml.h.
| #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) |
DCB DSCSR: Secure banked register select Mask
Definition at line 2966 of file core_armv81mml.h.
| #define DCB_DSCSR_SBRSELEN_Pos 0U |
DCB DSCSR: Secure banked register select enable Position
Definition at line 2968 of file core_armv81mml.h.
| #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) |
DCB DSCSR: Secure banked register select enable Mask
Definition at line 2969 of file core_armv81mml.h.
| #define DIB_DLAR_KEY_Pos 0U |
DIB DLAR: KEY Position
Definition at line 2995 of file core_armv81mml.h.
| #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) |
DIB DLAR: KEY Mask
Definition at line 2996 of file core_armv81mml.h.
| #define DIB_DLSR_nTT_Pos 2U |
DIB DLSR: Not thirty-two bit Position
Definition at line 2999 of file core_armv81mml.h.
| #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) |
DIB DLSR: Not thirty-two bit Mask
Definition at line 3000 of file core_armv81mml.h.
| #define DIB_DLSR_SLK_Pos 1U |
DIB DLSR: Software Lock status Position
Definition at line 3002 of file core_armv81mml.h.
| #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) |
DIB DLSR: Software Lock status Mask
Definition at line 3003 of file core_armv81mml.h.
| #define DIB_DLSR_SLI_Pos 0U |
DIB DLSR: Software Lock implemented Position
Definition at line 3005 of file core_armv81mml.h.
| #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) |
DIB DLSR: Software Lock implemented Mask
Definition at line 3006 of file core_armv81mml.h.
| #define DIB_DAUTHSTATUS_SNID_Pos 6U |
DIB DAUTHSTATUS: Secure Non-invasive Debug Position
Definition at line 3021 of file core_armv81mml.h.
| #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) |
DIB DAUTHSTATUS: Secure Non-invasive Debug Mask
Definition at line 3022 of file core_armv81mml.h.
| #define DIB_DAUTHSTATUS_SID_Pos 4U |
DIB DAUTHSTATUS: Secure Invasive Debug Position
Definition at line 3024 of file core_armv81mml.h.
| #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) |
DIB DAUTHSTATUS: Secure Invasive Debug Mask
Definition at line 3025 of file core_armv81mml.h.
| #define DIB_DAUTHSTATUS_NSNID_Pos 2U |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position
Definition at line 3027 of file core_armv81mml.h.
| #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask
Definition at line 3028 of file core_armv81mml.h.
| #define DIB_DAUTHSTATUS_NSID_Pos 0U |
DIB DAUTHSTATUS: Non-secure Invasive Debug Position
Definition at line 3030 of file core_armv81mml.h.
| #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) |
DIB DAUTHSTATUS: Non-secure Invasive Debug Mask
Definition at line 3031 of file core_armv81mml.h.
| #define DIB_DDEVARCH_ARCHITECT_Pos 21U |
DIB DDEVARCH: Architect Position
Definition at line 3034 of file core_armv81mml.h.
| #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) |
DIB DDEVARCH: Architect Mask
Definition at line 3035 of file core_armv81mml.h.
| #define DIB_DDEVARCH_PRESENT_Pos 20U |
DIB DDEVARCH: DEVARCH Present Position
Definition at line 3037 of file core_armv81mml.h.
| #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) |
DIB DDEVARCH: DEVARCH Present Mask
Definition at line 3038 of file core_armv81mml.h.
| #define DIB_DDEVARCH_REVISION_Pos 16U |
DIB DDEVARCH: Revision Position
Definition at line 3040 of file core_armv81mml.h.
| #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) |
DIB DDEVARCH: Revision Mask
Definition at line 3041 of file core_armv81mml.h.
| #define DIB_DDEVARCH_ARCHVER_Pos 12U |
DIB DDEVARCH: Architecture Version Position
Definition at line 3043 of file core_armv81mml.h.
| #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) |
DIB DDEVARCH: Architecture Version Mask
Definition at line 3044 of file core_armv81mml.h.
| #define DIB_DDEVARCH_ARCHPART_Pos 0U |
DIB DDEVARCH: Architecture Part Position
Definition at line 3046 of file core_armv81mml.h.
| #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) |
DIB DDEVARCH: Architecture Part Mask
Definition at line 3047 of file core_armv81mml.h.
| #define DIB_DDEVTYPE_SUB_Pos 4U |
DIB DDEVTYPE: Sub-type Position
Definition at line 3050 of file core_armv81mml.h.
| #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) |
DIB DDEVTYPE: Sub-type Mask
Definition at line 3051 of file core_armv81mml.h.
| #define DIB_DDEVTYPE_MAJOR_Pos 0U |
DIB DDEVTYPE: Major type Position
Definition at line 3053 of file core_armv81mml.h.
| #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) |
DIB DDEVTYPE: Major type Mask
Definition at line 3054 of file core_armv81mml.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 3073 of file core_armv81mml.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 3081 of file core_armv81mml.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 3094 of file core_armv81mml.h.
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
Definition at line 3095 of file core_armv81mml.h.
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
Definition at line 3096 of file core_armv81mml.h.
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
Definition at line 3097 of file core_armv81mml.h.
| #define DCB_BASE (0xE000EDF0UL) |
DCB Base Address
Definition at line 3099 of file core_armv81mml.h.
| #define DIB_BASE (0xE000EFB0UL) |
DIB Base Address
Definition at line 3100 of file core_armv81mml.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 3101 of file core_armv81mml.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 3102 of file core_armv81mml.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 3103 of file core_armv81mml.h.
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
Definition at line 3105 of file core_armv81mml.h.
SCB configuration struct
Definition at line 3106 of file core_armv81mml.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 3107 of file core_armv81mml.h.
NVIC configuration struct
Definition at line 3108 of file core_armv81mml.h.
ITM configuration struct
Definition at line 3109 of file core_armv81mml.h.
DWT configuration struct
Definition at line 3110 of file core_armv81mml.h.
TPI configuration struct
Definition at line 3111 of file core_armv81mml.h.
DCB configuration struct
Definition at line 3113 of file core_armv81mml.h.
DIB configuration struct
Definition at line 3114 of file core_armv81mml.h.
| #define MPU_BASE (SCS_BASE + 0x0D90UL) |
Memory Protection Unit
Definition at line 3117 of file core_armv81mml.h.
Memory Protection Unit
Definition at line 3118 of file core_armv81mml.h.
| #define FPU_BASE (SCS_BASE + 0x0F30UL) |
Floating Point Unit
Definition at line 3131 of file core_armv81mml.h.
Floating Point Unit
Definition at line 3132 of file core_armv81mml.h.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 4152 of file core_armv81mml.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 401 of file core_armv8mbl.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 402 of file core_armv8mbl.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 404 of file core_armv8mbl.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 405 of file core_armv8mbl.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 407 of file core_armv8mbl.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 408 of file core_armv8mbl.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 410 of file core_armv8mbl.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 411 of file core_armv8mbl.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 413 of file core_armv8mbl.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 414 of file core_armv8mbl.h.
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
Definition at line 417 of file core_armv8mbl.h.
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
Definition at line 418 of file core_armv8mbl.h.
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
Definition at line 420 of file core_armv8mbl.h.
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
Definition at line 421 of file core_armv8mbl.h.
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
Definition at line 423 of file core_armv8mbl.h.
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
Definition at line 424 of file core_armv8mbl.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 426 of file core_armv8mbl.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 427 of file core_armv8mbl.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 429 of file core_armv8mbl.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 430 of file core_armv8mbl.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 432 of file core_armv8mbl.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 433 of file core_armv8mbl.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 435 of file core_armv8mbl.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 436 of file core_armv8mbl.h.
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
Definition at line 438 of file core_armv8mbl.h.
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
Definition at line 439 of file core_armv8mbl.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 441 of file core_armv8mbl.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 442 of file core_armv8mbl.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 444 of file core_armv8mbl.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 445 of file core_armv8mbl.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 447 of file core_armv8mbl.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 448 of file core_armv8mbl.h.
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
Definition at line 450 of file core_armv8mbl.h.
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
Definition at line 451 of file core_armv8mbl.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 453 of file core_armv8mbl.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 454 of file core_armv8mbl.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 463 of file core_armv8mbl.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 464 of file core_armv8mbl.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 466 of file core_armv8mbl.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 467 of file core_armv8mbl.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 469 of file core_armv8mbl.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 470 of file core_armv8mbl.h.
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
Definition at line 472 of file core_armv8mbl.h.
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
Definition at line 473 of file core_armv8mbl.h.
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
Definition at line 475 of file core_armv8mbl.h.
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
Definition at line 476 of file core_armv8mbl.h.
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
Definition at line 478 of file core_armv8mbl.h.
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
Definition at line 479 of file core_armv8mbl.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 481 of file core_armv8mbl.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 482 of file core_armv8mbl.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 484 of file core_armv8mbl.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 485 of file core_armv8mbl.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 488 of file core_armv8mbl.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 489 of file core_armv8mbl.h.
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
Definition at line 491 of file core_armv8mbl.h.
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
Definition at line 492 of file core_armv8mbl.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 494 of file core_armv8mbl.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 495 of file core_armv8mbl.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 497 of file core_armv8mbl.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 498 of file core_armv8mbl.h.
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
SCB CCR: Branch prediction enable bit Position
Definition at line 501 of file core_armv8mbl.h.
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
SCB CCR: Branch prediction enable bit Mask
Definition at line 502 of file core_armv8mbl.h.
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
SCB CCR: Instruction cache enable bit Position
Definition at line 504 of file core_armv8mbl.h.
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
SCB CCR: Instruction cache enable bit Mask
Definition at line 505 of file core_armv8mbl.h.
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
SCB CCR: Cache enable bit Position
Definition at line 507 of file core_armv8mbl.h.
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
Definition at line 510 of file core_armv8mbl.h.
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
Definition at line 511 of file core_armv8mbl.h.
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
Definition at line 513 of file core_armv8mbl.h.
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
Definition at line 514 of file core_armv8mbl.h.
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
Definition at line 516 of file core_armv8mbl.h.
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
Definition at line 517 of file core_armv8mbl.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 519 of file core_armv8mbl.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 520 of file core_armv8mbl.h.
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
Definition at line 522 of file core_armv8mbl.h.
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
Definition at line 523 of file core_armv8mbl.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
Definition at line 526 of file core_armv8mbl.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
Definition at line 527 of file core_armv8mbl.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 529 of file core_armv8mbl.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 530 of file core_armv8mbl.h.
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
Definition at line 532 of file core_armv8mbl.h.
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
Definition at line 533 of file core_armv8mbl.h.
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
Definition at line 535 of file core_armv8mbl.h.
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
Definition at line 536 of file core_armv8mbl.h.
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
Definition at line 538 of file core_armv8mbl.h.
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
Definition at line 539 of file core_armv8mbl.h.
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
Definition at line 541 of file core_armv8mbl.h.
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
Definition at line 542 of file core_armv8mbl.h.
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
Definition at line 544 of file core_armv8mbl.h.
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
Definition at line 545 of file core_armv8mbl.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 569 of file core_armv8mbl.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 570 of file core_armv8mbl.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 572 of file core_armv8mbl.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 573 of file core_armv8mbl.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 575 of file core_armv8mbl.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 576 of file core_armv8mbl.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 578 of file core_armv8mbl.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 579 of file core_armv8mbl.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 582 of file core_armv8mbl.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 583 of file core_armv8mbl.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 586 of file core_armv8mbl.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 587 of file core_armv8mbl.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 590 of file core_armv8mbl.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 591 of file core_armv8mbl.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 593 of file core_armv8mbl.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 594 of file core_armv8mbl.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 596 of file core_armv8mbl.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 597 of file core_armv8mbl.h.
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
Definition at line 683 of file core_armv8mbl.h.
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
Definition at line 684 of file core_armv8mbl.h.
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
Definition at line 686 of file core_armv8mbl.h.
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
Definition at line 687 of file core_armv8mbl.h.
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
Definition at line 689 of file core_armv8mbl.h.
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
Definition at line 690 of file core_armv8mbl.h.
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
Definition at line 692 of file core_armv8mbl.h.
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
Definition at line 693 of file core_armv8mbl.h.
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
Definition at line 695 of file core_armv8mbl.h.
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
Definition at line 696 of file core_armv8mbl.h.
| #define DWT_FUNCTION_ID_Pos 27U |
DWT FUNCTION: ID Position
Definition at line 699 of file core_armv8mbl.h.
| #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) |
DWT FUNCTION: ID Mask
Definition at line 700 of file core_armv8mbl.h.
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
Definition at line 702 of file core_armv8mbl.h.
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
Definition at line 703 of file core_armv8mbl.h.
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
Definition at line 705 of file core_armv8mbl.h.
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
Definition at line 706 of file core_armv8mbl.h.
| #define DWT_FUNCTION_ACTION_Pos 4U |
DWT FUNCTION: ACTION Position
Definition at line 708 of file core_armv8mbl.h.
| #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) |
DWT FUNCTION: ACTION Mask
Definition at line 709 of file core_armv8mbl.h.
| #define DWT_FUNCTION_MATCH_Pos 0U |
DWT FUNCTION: MATCH Position
Definition at line 711 of file core_armv8mbl.h.
| #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) |
DWT FUNCTION: MATCH Mask
Definition at line 712 of file core_armv8mbl.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 752 of file core_armv8mbl.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 753 of file core_armv8mbl.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 756 of file core_armv8mbl.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 757 of file core_armv8mbl.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 759 of file core_armv8mbl.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 760 of file core_armv8mbl.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 762 of file core_armv8mbl.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 763 of file core_armv8mbl.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 765 of file core_armv8mbl.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 766 of file core_armv8mbl.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 769 of file core_armv8mbl.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 770 of file core_armv8mbl.h.
| #define TPI_FFCR_FOnMan_Pos 6U |
TPI FFCR: FOnMan Position
Definition at line 772 of file core_armv8mbl.h.
| #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) |
TPI FFCR: FOnMan Mask
Definition at line 773 of file core_armv8mbl.h.
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
Definition at line 775 of file core_armv8mbl.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 776 of file core_armv8mbl.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 793 of file core_armv8mbl.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 794 of file core_armv8mbl.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 796 of file core_armv8mbl.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 797 of file core_armv8mbl.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 799 of file core_armv8mbl.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 800 of file core_armv8mbl.h.
| #define TPI_DEVID_FIFOSZ_Pos 6U |
TPI DEVID: FIFO depth Position
TPI DEVID: FIFOSZ Position
Definition at line 802 of file core_armv8mbl.h.
| #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) |
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
Definition at line 806 of file core_armv8mbl.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 807 of file core_armv8mbl.h.
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
Definition at line 809 of file core_armv8mbl.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 810 of file core_armv8mbl.h.
| #define MPU_TYPE_IREGION_Pos 16U |
MPU TYPE: IREGION Position
Definition at line 846 of file core_armv8mbl.h.
| #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) |
MPU TYPE: IREGION Mask
Definition at line 847 of file core_armv8mbl.h.
| #define MPU_TYPE_DREGION_Pos 8U |
MPU TYPE: DREGION Position
Definition at line 849 of file core_armv8mbl.h.
| #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) |
MPU TYPE: DREGION Mask
Definition at line 850 of file core_armv8mbl.h.
| #define MPU_TYPE_SEPARATE_Pos 0U |
MPU TYPE: SEPARATE Position
Definition at line 852 of file core_armv8mbl.h.
| #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) |
MPU TYPE: SEPARATE Mask
Definition at line 853 of file core_armv8mbl.h.
| #define MPU_CTRL_PRIVDEFENA_Pos 2U |
MPU CTRL: PRIVDEFENA Position
Definition at line 856 of file core_armv8mbl.h.
| #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) |
MPU CTRL: PRIVDEFENA Mask
Definition at line 857 of file core_armv8mbl.h.
| #define MPU_CTRL_HFNMIENA_Pos 1U |
MPU CTRL: HFNMIENA Position
Definition at line 859 of file core_armv8mbl.h.
| #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) |
MPU CTRL: HFNMIENA Mask
Definition at line 860 of file core_armv8mbl.h.
| #define MPU_CTRL_ENABLE_Pos 0U |
MPU CTRL: ENABLE Position
Definition at line 862 of file core_armv8mbl.h.
| #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) |
MPU CTRL: ENABLE Mask
Definition at line 863 of file core_armv8mbl.h.
| #define MPU_RNR_REGION_Pos 0U |
MPU RNR: REGION Position
Definition at line 866 of file core_armv8mbl.h.
| #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) |
MPU RNR: REGION Mask
Definition at line 867 of file core_armv8mbl.h.
| #define MPU_RBAR_BASE_Pos 5U |
MPU RBAR: BASE Position
Definition at line 870 of file core_armv8mbl.h.
| #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) |
MPU RBAR: BASE Mask
Definition at line 871 of file core_armv8mbl.h.
| #define MPU_RBAR_SH_Pos 3U |
MPU RBAR: SH Position
Definition at line 873 of file core_armv8mbl.h.
| #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) |
MPU RBAR: SH Mask
Definition at line 874 of file core_armv8mbl.h.
| #define MPU_RBAR_AP_Pos 1U |
MPU RBAR: AP Position
Definition at line 876 of file core_armv8mbl.h.
| #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) |
MPU RBAR: AP Mask
Definition at line 877 of file core_armv8mbl.h.
| #define MPU_RBAR_XN_Pos 0U |
MPU RBAR: XN Position
Definition at line 879 of file core_armv8mbl.h.
| #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) |
MPU RBAR: XN Mask
Definition at line 880 of file core_armv8mbl.h.
| #define MPU_RLAR_LIMIT_Pos 5U |
MPU RLAR: LIMIT Position
Definition at line 883 of file core_armv8mbl.h.
| #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) |
MPU RLAR: LIMIT Mask
Definition at line 884 of file core_armv8mbl.h.
| #define MPU_RLAR_AttrIndx_Pos 1U |
MPU RLAR: AttrIndx Position
Definition at line 886 of file core_armv8mbl.h.
| #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) |
MPU RLAR: AttrIndx Mask
Definition at line 887 of file core_armv8mbl.h.
| #define MPU_RLAR_EN_Pos 0U |
MPU RLAR: EN Position
MPU RLAR: Region enable bit Position
Definition at line 889 of file core_armv8mbl.h.
| #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) |
MPU RLAR: EN Mask
MPU RLAR: Region enable bit Disable Mask
Definition at line 890 of file core_armv8mbl.h.
| #define MPU_MAIR0_Attr3_Pos 24U |
MPU MAIR0: Attr3 Position
Definition at line 893 of file core_armv8mbl.h.
| #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) |
MPU MAIR0: Attr3 Mask
Definition at line 894 of file core_armv8mbl.h.
| #define MPU_MAIR0_Attr2_Pos 16U |
MPU MAIR0: Attr2 Position
Definition at line 896 of file core_armv8mbl.h.
| #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) |
MPU MAIR0: Attr2 Mask
Definition at line 897 of file core_armv8mbl.h.
| #define MPU_MAIR0_Attr1_Pos 8U |
MPU MAIR0: Attr1 Position
Definition at line 899 of file core_armv8mbl.h.
| #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) |
MPU MAIR0: Attr1 Mask
Definition at line 900 of file core_armv8mbl.h.
| #define MPU_MAIR0_Attr0_Pos 0U |
MPU MAIR0: Attr0 Position
Definition at line 902 of file core_armv8mbl.h.
| #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) |
MPU MAIR0: Attr0 Mask
Definition at line 903 of file core_armv8mbl.h.
| #define MPU_MAIR1_Attr7_Pos 24U |
MPU MAIR1: Attr7 Position
Definition at line 906 of file core_armv8mbl.h.
| #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) |
MPU MAIR1: Attr7 Mask
Definition at line 907 of file core_armv8mbl.h.
| #define MPU_MAIR1_Attr6_Pos 16U |
MPU MAIR1: Attr6 Position
Definition at line 909 of file core_armv8mbl.h.
| #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) |
MPU MAIR1: Attr6 Mask
Definition at line 910 of file core_armv8mbl.h.
| #define MPU_MAIR1_Attr5_Pos 8U |
MPU MAIR1: Attr5 Position
Definition at line 912 of file core_armv8mbl.h.
| #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) |
MPU MAIR1: Attr5 Mask
Definition at line 913 of file core_armv8mbl.h.
| #define MPU_MAIR1_Attr4_Pos 0U |
MPU MAIR1: Attr4 Position
Definition at line 915 of file core_armv8mbl.h.
| #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) |
MPU MAIR1: Attr4 Mask
Definition at line 916 of file core_armv8mbl.h.
| #define DCB_DHCSR_DBGKEY_Pos 16U |
DCB DHCSR: Debug key Position
Definition at line 1104 of file core_armv8mbl.h.
| #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) |
DCB DHCSR: Debug key Mask
Definition at line 1105 of file core_armv8mbl.h.
| #define DCB_DHCSR_S_RESTART_ST_Pos 26U |
DCB DHCSR: Restart sticky status Position
Definition at line 1107 of file core_armv8mbl.h.
| #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) |
DCB DHCSR: Restart sticky status Mask
Definition at line 1108 of file core_armv8mbl.h.
| #define DCB_DHCSR_S_RESET_ST_Pos 25U |
DCB DHCSR: Reset sticky status Position
Definition at line 1110 of file core_armv8mbl.h.
| #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) |
DCB DHCSR: Reset sticky status Mask
Definition at line 1111 of file core_armv8mbl.h.
| #define DCB_DHCSR_S_RETIRE_ST_Pos 24U |
DCB DHCSR: Retire sticky status Position
Definition at line 1113 of file core_armv8mbl.h.
| #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) |
DCB DHCSR: Retire sticky status Mask
Definition at line 1114 of file core_armv8mbl.h.
| #define DCB_DHCSR_S_SDE_Pos 20U |
DCB DHCSR: Secure debug enabled Position
Definition at line 1116 of file core_armv8mbl.h.
| #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) |
DCB DHCSR: Secure debug enabled Mask
Definition at line 1117 of file core_armv8mbl.h.
| #define DCB_DHCSR_S_LOCKUP_Pos 19U |
DCB DHCSR: Lockup status Position
Definition at line 1119 of file core_armv8mbl.h.
| #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) |
DCB DHCSR: Lockup status Mask
Definition at line 1120 of file core_armv8mbl.h.
| #define DCB_DHCSR_S_SLEEP_Pos 18U |
DCB DHCSR: Sleeping status Position
Definition at line 1122 of file core_armv8mbl.h.
| #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) |
DCB DHCSR: Sleeping status Mask
Definition at line 1123 of file core_armv8mbl.h.
| #define DCB_DHCSR_S_HALT_Pos 17U |
DCB DHCSR: Halted status Position
Definition at line 1125 of file core_armv8mbl.h.
| #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) |
DCB DHCSR: Halted status Mask
Definition at line 1126 of file core_armv8mbl.h.
| #define DCB_DHCSR_S_REGRDY_Pos 16U |
DCB DHCSR: Register ready status Position
Definition at line 1128 of file core_armv8mbl.h.
| #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) |
DCB DHCSR: Register ready status Mask
Definition at line 1129 of file core_armv8mbl.h.
| #define DCB_DHCSR_C_MASKINTS_Pos 3U |
DCB DHCSR: Mask interrupts control Position
Definition at line 1131 of file core_armv8mbl.h.
| #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) |
DCB DHCSR: Mask interrupts control Mask
Definition at line 1132 of file core_armv8mbl.h.
| #define DCB_DHCSR_C_STEP_Pos 2U |
DCB DHCSR: Step control Position
Definition at line 1134 of file core_armv8mbl.h.
| #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) |
DCB DHCSR: Step control Mask
Definition at line 1135 of file core_armv8mbl.h.
| #define DCB_DHCSR_C_HALT_Pos 1U |
DCB DHCSR: Halt control Position
Definition at line 1137 of file core_armv8mbl.h.
| #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) |
DCB DHCSR: Halt control Mask
Definition at line 1138 of file core_armv8mbl.h.
| #define DCB_DHCSR_C_DEBUGEN_Pos 0U |
DCB DHCSR: Debug enable control Position
Definition at line 1140 of file core_armv8mbl.h.
| #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) |
DCB DHCSR: Debug enable control Mask
Definition at line 1141 of file core_armv8mbl.h.
| #define DCB_DCRSR_REGWnR_Pos 16U |
DCB DCRSR: Register write/not-read Position
Definition at line 1144 of file core_armv8mbl.h.
| #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) |
DCB DCRSR: Register write/not-read Mask
Definition at line 1145 of file core_armv8mbl.h.
| #define DCB_DCRSR_REGSEL_Pos 0U |
DCB DCRSR: Register selector Position
Definition at line 1147 of file core_armv8mbl.h.
| #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) |
DCB DCRSR: Register selector Mask
Definition at line 1148 of file core_armv8mbl.h.
| #define DCB_DCRDR_DBGTMP_Pos 0U |
DCB DCRDR: Data temporary buffer Position
Definition at line 1151 of file core_armv8mbl.h.
| #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) |
DCB DCRDR: Data temporary buffer Mask
Definition at line 1152 of file core_armv8mbl.h.
| #define DCB_DEMCR_TRCENA_Pos 24U |
DCB DEMCR: Trace enable Position
Definition at line 1155 of file core_armv8mbl.h.
| #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) |
DCB DEMCR: Trace enable Mask
Definition at line 1156 of file core_armv8mbl.h.
| #define DCB_DEMCR_VC_HARDERR_Pos 10U |
DCB DEMCR: Vector Catch HardFault errors Position
Definition at line 1158 of file core_armv8mbl.h.
| #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) |
DCB DEMCR: Vector Catch HardFault errors Mask
Definition at line 1159 of file core_armv8mbl.h.
| #define DCB_DEMCR_VC_CORERESET_Pos 0U |
DCB DEMCR: Vector Catch Core reset Position
Definition at line 1161 of file core_armv8mbl.h.
| #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) |
DCB DEMCR: Vector Catch Core reset Mask
Definition at line 1162 of file core_armv8mbl.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position
Definition at line 1165 of file core_armv8mbl.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask
Definition at line 1166 of file core_armv8mbl.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U |
DCB DAUTHCTRL: Secure non-invasive debug enable select Position
Definition at line 1168 of file core_armv8mbl.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) |
DCB DAUTHCTRL: Secure non-invasive debug enable select Mask
Definition at line 1169 of file core_armv8mbl.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U |
DCB DAUTHCTRL: Internal Secure invasive debug enable Position
Definition at line 1171 of file core_armv8mbl.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure invasive debug enable Mask
Definition at line 1172 of file core_armv8mbl.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U |
DCB DAUTHCTRL: Secure invasive debug enable select Position
Definition at line 1174 of file core_armv8mbl.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) |
DCB DAUTHCTRL: Secure invasive debug enable select Mask
Definition at line 1175 of file core_armv8mbl.h.
| #define DCB_DSCSR_CDSKEY_Pos 17U |
DCB DSCSR: CDS write-enable key Position
Definition at line 1178 of file core_armv8mbl.h.
| #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) |
DCB DSCSR: CDS write-enable key Mask
Definition at line 1179 of file core_armv8mbl.h.
| #define DCB_DSCSR_CDS_Pos 16U |
DCB DSCSR: Current domain Secure Position
Definition at line 1181 of file core_armv8mbl.h.
| #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) |
DCB DSCSR: Current domain Secure Mask
Definition at line 1182 of file core_armv8mbl.h.
| #define DCB_DSCSR_SBRSEL_Pos 1U |
DCB DSCSR: Secure banked register select Position
Definition at line 1184 of file core_armv8mbl.h.
| #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) |
DCB DSCSR: Secure banked register select Mask
Definition at line 1185 of file core_armv8mbl.h.
| #define DCB_DSCSR_SBRSELEN_Pos 0U |
DCB DSCSR: Secure banked register select enable Position
Definition at line 1187 of file core_armv8mbl.h.
| #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) |
DCB DSCSR: Secure banked register select enable Mask
Definition at line 1188 of file core_armv8mbl.h.
| #define DIB_DLAR_KEY_Pos 0U |
DIB DLAR: KEY Position
Definition at line 1214 of file core_armv8mbl.h.
| #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) |
DIB DLAR: KEY Mask
Definition at line 1215 of file core_armv8mbl.h.
| #define DIB_DLSR_nTT_Pos 2U |
DIB DLSR: Not thirty-two bit Position
Definition at line 1218 of file core_armv8mbl.h.
| #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) |
DIB DLSR: Not thirty-two bit Mask
Definition at line 1219 of file core_armv8mbl.h.
| #define DIB_DLSR_SLK_Pos 1U |
DIB DLSR: Software Lock status Position
Definition at line 1221 of file core_armv8mbl.h.
| #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) |
DIB DLSR: Software Lock status Mask
Definition at line 1222 of file core_armv8mbl.h.
| #define DIB_DLSR_SLI_Pos 0U |
DIB DLSR: Software Lock implemented Position
Definition at line 1224 of file core_armv8mbl.h.
| #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) |
DIB DLSR: Software Lock implemented Mask
Definition at line 1225 of file core_armv8mbl.h.
| #define DIB_DAUTHSTATUS_SNID_Pos 6U |
DIB DAUTHSTATUS: Secure Non-invasive Debug Position
Definition at line 1228 of file core_armv8mbl.h.
| #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) |
DIB DAUTHSTATUS: Secure Non-invasive Debug Mask
Definition at line 1229 of file core_armv8mbl.h.
| #define DIB_DAUTHSTATUS_SID_Pos 4U |
DIB DAUTHSTATUS: Secure Invasive Debug Position
Definition at line 1231 of file core_armv8mbl.h.
| #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) |
DIB DAUTHSTATUS: Secure Invasive Debug Mask
Definition at line 1232 of file core_armv8mbl.h.
| #define DIB_DAUTHSTATUS_NSNID_Pos 2U |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position
Definition at line 1234 of file core_armv8mbl.h.
| #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask
Definition at line 1235 of file core_armv8mbl.h.
| #define DIB_DAUTHSTATUS_NSID_Pos 0U |
DIB DAUTHSTATUS: Non-secure Invasive Debug Position
Definition at line 1237 of file core_armv8mbl.h.
| #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) |
DIB DAUTHSTATUS: Non-secure Invasive Debug Mask
Definition at line 1238 of file core_armv8mbl.h.
| #define DIB_DDEVARCH_ARCHITECT_Pos 21U |
DIB DDEVARCH: Architect Position
Definition at line 1241 of file core_armv8mbl.h.
| #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) |
DIB DDEVARCH: Architect Mask
Definition at line 1242 of file core_armv8mbl.h.
| #define DIB_DDEVARCH_PRESENT_Pos 20U |
DIB DDEVARCH: DEVARCH Present Position
Definition at line 1244 of file core_armv8mbl.h.
| #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) |
DIB DDEVARCH: DEVARCH Present Mask
Definition at line 1245 of file core_armv8mbl.h.
| #define DIB_DDEVARCH_REVISION_Pos 16U |
DIB DDEVARCH: Revision Position
Definition at line 1247 of file core_armv8mbl.h.
| #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) |
DIB DDEVARCH: Revision Mask
Definition at line 1248 of file core_armv8mbl.h.
| #define DIB_DDEVARCH_ARCHVER_Pos 12U |
DIB DDEVARCH: Architecture Version Position
Definition at line 1250 of file core_armv8mbl.h.
| #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) |
DIB DDEVARCH: Architecture Version Mask
Definition at line 1251 of file core_armv8mbl.h.
| #define DIB_DDEVARCH_ARCHPART_Pos 0U |
DIB DDEVARCH: Architecture Part Position
Definition at line 1253 of file core_armv8mbl.h.
| #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) |
DIB DDEVARCH: Architecture Part Mask
Definition at line 1254 of file core_armv8mbl.h.
| #define DIB_DDEVTYPE_SUB_Pos 4U |
DIB DDEVTYPE: Sub-type Position
Definition at line 1257 of file core_armv8mbl.h.
| #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) |
DIB DDEVTYPE: Sub-type Mask
Definition at line 1258 of file core_armv8mbl.h.
| #define DIB_DDEVTYPE_MAJOR_Pos 0U |
DIB DDEVTYPE: Major type Position
Definition at line 1260 of file core_armv8mbl.h.
| #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) |
DIB DDEVTYPE: Major type Mask
Definition at line 1261 of file core_armv8mbl.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 1280 of file core_armv8mbl.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 1288 of file core_armv8mbl.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 1301 of file core_armv8mbl.h.
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
Definition at line 1302 of file core_armv8mbl.h.
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
Definition at line 1303 of file core_armv8mbl.h.
| #define DCB_BASE (0xE000EDF0UL) |
DCB Base Address
Definition at line 1305 of file core_armv8mbl.h.
| #define DIB_BASE (0xE000EFB0UL) |
DIB Base Address
Definition at line 1306 of file core_armv8mbl.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 1307 of file core_armv8mbl.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 1308 of file core_armv8mbl.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 1309 of file core_armv8mbl.h.
SCB configuration struct
Definition at line 1312 of file core_armv8mbl.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 1313 of file core_armv8mbl.h.
NVIC configuration struct
Definition at line 1314 of file core_armv8mbl.h.
DWT configuration struct
Definition at line 1315 of file core_armv8mbl.h.
TPI configuration struct
Definition at line 1316 of file core_armv8mbl.h.
DCB configuration struct
Definition at line 1318 of file core_armv8mbl.h.
DIB configuration struct
Definition at line 1319 of file core_armv8mbl.h.
| #define MPU_BASE (SCS_BASE + 0x0D90UL) |
Memory Protection Unit
Definition at line 1322 of file core_armv8mbl.h.
Memory Protection Unit
Definition at line 1323 of file core_armv8mbl.h.
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
Definition at line 488 of file core_armv8mml.h.
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
Definition at line 489 of file core_armv8mml.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 555 of file core_armv8mml.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 556 of file core_armv8mml.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 558 of file core_armv8mml.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 559 of file core_armv8mml.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 561 of file core_armv8mml.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 562 of file core_armv8mml.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 564 of file core_armv8mml.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 565 of file core_armv8mml.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 567 of file core_armv8mml.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 568 of file core_armv8mml.h.
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
Definition at line 571 of file core_armv8mml.h.
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
Definition at line 572 of file core_armv8mml.h.
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
Definition at line 574 of file core_armv8mml.h.
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
Definition at line 575 of file core_armv8mml.h.
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
Definition at line 577 of file core_armv8mml.h.
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
Definition at line 578 of file core_armv8mml.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 580 of file core_armv8mml.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 581 of file core_armv8mml.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 583 of file core_armv8mml.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 584 of file core_armv8mml.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 586 of file core_armv8mml.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 587 of file core_armv8mml.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 589 of file core_armv8mml.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 590 of file core_armv8mml.h.
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
Definition at line 592 of file core_armv8mml.h.
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
Definition at line 593 of file core_armv8mml.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 595 of file core_armv8mml.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 596 of file core_armv8mml.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 598 of file core_armv8mml.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 599 of file core_armv8mml.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 601 of file core_armv8mml.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 602 of file core_armv8mml.h.
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
Definition at line 604 of file core_armv8mml.h.
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
Definition at line 605 of file core_armv8mml.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 607 of file core_armv8mml.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 608 of file core_armv8mml.h.
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
Definition at line 611 of file core_armv8mml.h.
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
Definition at line 612 of file core_armv8mml.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 615 of file core_armv8mml.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 616 of file core_armv8mml.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 618 of file core_armv8mml.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 619 of file core_armv8mml.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 621 of file core_armv8mml.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 622 of file core_armv8mml.h.
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
Definition at line 624 of file core_armv8mml.h.
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
Definition at line 625 of file core_armv8mml.h.
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
Definition at line 627 of file core_armv8mml.h.
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
Definition at line 628 of file core_armv8mml.h.
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
Definition at line 630 of file core_armv8mml.h.
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
Definition at line 631 of file core_armv8mml.h.
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
Definition at line 633 of file core_armv8mml.h.
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
Definition at line 634 of file core_armv8mml.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 636 of file core_armv8mml.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 637 of file core_armv8mml.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 639 of file core_armv8mml.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 640 of file core_armv8mml.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 643 of file core_armv8mml.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 644 of file core_armv8mml.h.
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
Definition at line 646 of file core_armv8mml.h.
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
Definition at line 647 of file core_armv8mml.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 649 of file core_armv8mml.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 650 of file core_armv8mml.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 652 of file core_armv8mml.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 653 of file core_armv8mml.h.
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
SCB CCR: Branch prediction enable bit Position
Definition at line 656 of file core_armv8mml.h.
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
SCB CCR: Branch prediction enable bit Mask
Definition at line 657 of file core_armv8mml.h.
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
SCB CCR: Instruction cache enable bit Position
Definition at line 659 of file core_armv8mml.h.
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
SCB CCR: Instruction cache enable bit Mask
Definition at line 660 of file core_armv8mml.h.
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
SCB CCR: Cache enable bit Position
Definition at line 662 of file core_armv8mml.h.
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
Definition at line 665 of file core_armv8mml.h.
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
Definition at line 666 of file core_armv8mml.h.
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
Definition at line 668 of file core_armv8mml.h.
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
Definition at line 669 of file core_armv8mml.h.
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
Definition at line 671 of file core_armv8mml.h.
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
Definition at line 672 of file core_armv8mml.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 674 of file core_armv8mml.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 675 of file core_armv8mml.h.
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
Definition at line 677 of file core_armv8mml.h.
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
Definition at line 678 of file core_armv8mml.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
Definition at line 681 of file core_armv8mml.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
Definition at line 682 of file core_armv8mml.h.
| #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
SCB SHCSR: SECUREFAULTPENDED Position
Definition at line 684 of file core_armv8mml.h.
| #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
SCB SHCSR: SECUREFAULTPENDED Mask
Definition at line 685 of file core_armv8mml.h.
| #define SCB_SHCSR_SECUREFAULTENA_Pos 19U |
SCB SHCSR: SECUREFAULTENA Position
Definition at line 687 of file core_armv8mml.h.
| #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
SCB SHCSR: SECUREFAULTENA Mask
Definition at line 688 of file core_armv8mml.h.
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
Definition at line 690 of file core_armv8mml.h.
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
Definition at line 691 of file core_armv8mml.h.
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
Definition at line 693 of file core_armv8mml.h.
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
Definition at line 694 of file core_armv8mml.h.
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
Definition at line 696 of file core_armv8mml.h.
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
Definition at line 697 of file core_armv8mml.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 699 of file core_armv8mml.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 700 of file core_armv8mml.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
Definition at line 702 of file core_armv8mml.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
Definition at line 703 of file core_armv8mml.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
Definition at line 705 of file core_armv8mml.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
Definition at line 706 of file core_armv8mml.h.
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
Definition at line 708 of file core_armv8mml.h.
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
Definition at line 709 of file core_armv8mml.h.
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
Definition at line 711 of file core_armv8mml.h.
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
Definition at line 712 of file core_armv8mml.h.
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
Definition at line 714 of file core_armv8mml.h.
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
Definition at line 715 of file core_armv8mml.h.
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
Definition at line 717 of file core_armv8mml.h.
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
Definition at line 718 of file core_armv8mml.h.
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
Definition at line 720 of file core_armv8mml.h.
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
Definition at line 721 of file core_armv8mml.h.
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
Definition at line 723 of file core_armv8mml.h.
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
Definition at line 724 of file core_armv8mml.h.
| #define SCB_SHCSR_SECUREFAULTACT_Pos 4U |
SCB SHCSR: SECUREFAULTACT Position
Definition at line 726 of file core_armv8mml.h.
| #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
SCB SHCSR: SECUREFAULTACT Mask
Definition at line 727 of file core_armv8mml.h.
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
Definition at line 729 of file core_armv8mml.h.
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
Definition at line 730 of file core_armv8mml.h.
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
Definition at line 732 of file core_armv8mml.h.
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
Definition at line 733 of file core_armv8mml.h.
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
Definition at line 735 of file core_armv8mml.h.
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
Definition at line 736 of file core_armv8mml.h.
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
Definition at line 738 of file core_armv8mml.h.
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
Definition at line 739 of file core_armv8mml.h.
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
Definition at line 742 of file core_armv8mml.h.
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
Definition at line 743 of file core_armv8mml.h.
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
Definition at line 745 of file core_armv8mml.h.
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
Definition at line 746 of file core_armv8mml.h.
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
Definition at line 748 of file core_armv8mml.h.
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
Definition at line 749 of file core_armv8mml.h.
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
Definition at line 752 of file core_armv8mml.h.
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
Definition at line 753 of file core_armv8mml.h.
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
Definition at line 755 of file core_armv8mml.h.
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
Definition at line 756 of file core_armv8mml.h.
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
Definition at line 758 of file core_armv8mml.h.
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
Definition at line 759 of file core_armv8mml.h.
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
Definition at line 761 of file core_armv8mml.h.
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
Definition at line 762 of file core_armv8mml.h.
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
Definition at line 764 of file core_armv8mml.h.
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
Definition at line 765 of file core_armv8mml.h.
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
Definition at line 767 of file core_armv8mml.h.
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
Definition at line 768 of file core_armv8mml.h.
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
Definition at line 771 of file core_armv8mml.h.
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
Definition at line 772 of file core_armv8mml.h.
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
Definition at line 774 of file core_armv8mml.h.
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
Definition at line 775 of file core_armv8mml.h.
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
Definition at line 777 of file core_armv8mml.h.
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
Definition at line 778 of file core_armv8mml.h.
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
Definition at line 780 of file core_armv8mml.h.
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
Definition at line 781 of file core_armv8mml.h.
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
Definition at line 783 of file core_armv8mml.h.
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
Definition at line 784 of file core_armv8mml.h.
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
Definition at line 786 of file core_armv8mml.h.
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
Definition at line 787 of file core_armv8mml.h.
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
Definition at line 789 of file core_armv8mml.h.
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
Definition at line 790 of file core_armv8mml.h.
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
Definition at line 793 of file core_armv8mml.h.
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
Definition at line 794 of file core_armv8mml.h.
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
Definition at line 796 of file core_armv8mml.h.
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
Definition at line 797 of file core_armv8mml.h.
| #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
SCB CFSR (UFSR): STKOF Position
Definition at line 799 of file core_armv8mml.h.
| #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
SCB CFSR (UFSR): STKOF Mask
Definition at line 800 of file core_armv8mml.h.
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
Definition at line 802 of file core_armv8mml.h.
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
Definition at line 803 of file core_armv8mml.h.
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
Definition at line 805 of file core_armv8mml.h.
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
Definition at line 806 of file core_armv8mml.h.
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
Definition at line 808 of file core_armv8mml.h.
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
Definition at line 809 of file core_armv8mml.h.
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
Definition at line 811 of file core_armv8mml.h.
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
Definition at line 812 of file core_armv8mml.h.
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
Definition at line 815 of file core_armv8mml.h.
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
Definition at line 816 of file core_armv8mml.h.
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
Definition at line 818 of file core_armv8mml.h.
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
Definition at line 819 of file core_armv8mml.h.
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
Definition at line 821 of file core_armv8mml.h.
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
Definition at line 822 of file core_armv8mml.h.
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
Definition at line 825 of file core_armv8mml.h.
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
Definition at line 826 of file core_armv8mml.h.
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
Definition at line 828 of file core_armv8mml.h.
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
Definition at line 829 of file core_armv8mml.h.
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
Definition at line 831 of file core_armv8mml.h.
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
Definition at line 832 of file core_armv8mml.h.
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
Definition at line 834 of file core_armv8mml.h.
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
Definition at line 835 of file core_armv8mml.h.
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
Definition at line 837 of file core_armv8mml.h.
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
Definition at line 838 of file core_armv8mml.h.
| #define SCB_NSACR_CP11_Pos 11U |
SCB NSACR: CP11 Position
Definition at line 841 of file core_armv8mml.h.
| #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
SCB NSACR: CP11 Mask
Definition at line 842 of file core_armv8mml.h.
| #define SCB_NSACR_CP10_Pos 10U |
SCB NSACR: CP10 Position
Definition at line 844 of file core_armv8mml.h.
| #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
SCB NSACR: CP10 Mask
Definition at line 845 of file core_armv8mml.h.
| #define SCB_NSACR_CPn_Pos 0U |
SCB NSACR: CPn Position
Definition at line 847 of file core_armv8mml.h.
| #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) |
SCB NSACR: CPn Mask
Definition at line 848 of file core_armv8mml.h.
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
Definition at line 851 of file core_armv8mml.h.
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
Definition at line 852 of file core_armv8mml.h.
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
Definition at line 854 of file core_armv8mml.h.
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
Definition at line 855 of file core_armv8mml.h.
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
Definition at line 858 of file core_armv8mml.h.
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
Definition at line 859 of file core_armv8mml.h.
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
Definition at line 861 of file core_armv8mml.h.
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
Definition at line 862 of file core_armv8mml.h.
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
Definition at line 864 of file core_armv8mml.h.
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
Definition at line 865 of file core_armv8mml.h.
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
Definition at line 867 of file core_armv8mml.h.
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
Definition at line 868 of file core_armv8mml.h.
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
Definition at line 870 of file core_armv8mml.h.
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
Definition at line 871 of file core_armv8mml.h.
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
Definition at line 874 of file core_armv8mml.h.
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
Definition at line 875 of file core_armv8mml.h.
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
Definition at line 877 of file core_armv8mml.h.
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
Definition at line 878 of file core_armv8mml.h.
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
Definition at line 880 of file core_armv8mml.h.
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
Definition at line 881 of file core_armv8mml.h.
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
Definition at line 883 of file core_armv8mml.h.
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
Definition at line 884 of file core_armv8mml.h.
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
Definition at line 886 of file core_armv8mml.h.
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
Definition at line 887 of file core_armv8mml.h.
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
Definition at line 889 of file core_armv8mml.h.
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
Definition at line 890 of file core_armv8mml.h.
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
Definition at line 892 of file core_armv8mml.h.
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
Definition at line 893 of file core_armv8mml.h.
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
Definition at line 896 of file core_armv8mml.h.
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
Definition at line 897 of file core_armv8mml.h.
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
Definition at line 899 of file core_armv8mml.h.
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
Definition at line 900 of file core_armv8mml.h.
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
Definition at line 903 of file core_armv8mml.h.
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
Definition at line 904 of file core_armv8mml.h.
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
Definition at line 907 of file core_armv8mml.h.
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
Definition at line 908 of file core_armv8mml.h.
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
Definition at line 910 of file core_armv8mml.h.
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
Definition at line 911 of file core_armv8mml.h.
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
Definition at line 914 of file core_armv8mml.h.
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
Definition at line 915 of file core_armv8mml.h.
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
Definition at line 917 of file core_armv8mml.h.
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
Definition at line 918 of file core_armv8mml.h.
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
Definition at line 921 of file core_armv8mml.h.
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
Definition at line 922 of file core_armv8mml.h.
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
Definition at line 924 of file core_armv8mml.h.
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
Definition at line 925 of file core_armv8mml.h.
| #define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
Definition at line 949 of file core_armv8mml.h.
| #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
Definition at line 950 of file core_armv8mml.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 974 of file core_armv8mml.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 975 of file core_armv8mml.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 977 of file core_armv8mml.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 978 of file core_armv8mml.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 980 of file core_armv8mml.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 981 of file core_armv8mml.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 983 of file core_armv8mml.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 984 of file core_armv8mml.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 987 of file core_armv8mml.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 988 of file core_armv8mml.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 991 of file core_armv8mml.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 992 of file core_armv8mml.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 995 of file core_armv8mml.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 996 of file core_armv8mml.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 998 of file core_armv8mml.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 999 of file core_armv8mml.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 1001 of file core_armv8mml.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 1002 of file core_armv8mml.h.
| #define ITM_STIM_DISABLED_Pos 1U |
ITM STIM: DISABLED Position
Definition at line 1053 of file core_armv8mml.h.
| #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) |
ITM STIM: DISABLED Mask
Definition at line 1054 of file core_armv8mml.h.
| #define ITM_STIM_FIFOREADY_Pos 0U |
ITM STIM: FIFOREADY Position
Definition at line 1056 of file core_armv8mml.h.
| #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) |
ITM STIM: FIFOREADY Mask
Definition at line 1057 of file core_armv8mml.h.
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
Definition at line 1060 of file core_armv8mml.h.
| #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
Definition at line 1061 of file core_armv8mml.h.
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
Definition at line 1064 of file core_armv8mml.h.
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
Definition at line 1065 of file core_armv8mml.h.
| #define ITM_TCR_TRACEBUSID_Pos 16U |
ITM TCR: ATBID Position
Definition at line 1067 of file core_armv8mml.h.
| #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) |
ITM TCR: ATBID Mask
Definition at line 1068 of file core_armv8mml.h.
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
Definition at line 1070 of file core_armv8mml.h.
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
Definition at line 1071 of file core_armv8mml.h.
| #define ITM_TCR_TSPRESCALE_Pos 8U |
ITM TCR: TSPRESCALE Position
Definition at line 1073 of file core_armv8mml.h.
| #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) |
ITM TCR: TSPRESCALE Mask
Definition at line 1074 of file core_armv8mml.h.
| #define ITM_TCR_STALLENA_Pos 5U |
ITM TCR: STALLENA Position
Definition at line 1076 of file core_armv8mml.h.
| #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) |
ITM TCR: STALLENA Mask
Definition at line 1077 of file core_armv8mml.h.
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
Definition at line 1079 of file core_armv8mml.h.
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
Definition at line 1080 of file core_armv8mml.h.
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
Definition at line 1082 of file core_armv8mml.h.
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
Definition at line 1083 of file core_armv8mml.h.
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
Definition at line 1085 of file core_armv8mml.h.
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
Definition at line 1086 of file core_armv8mml.h.
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
Definition at line 1088 of file core_armv8mml.h.
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
Definition at line 1089 of file core_armv8mml.h.
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
Definition at line 1091 of file core_armv8mml.h.
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
Definition at line 1092 of file core_armv8mml.h.
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
Definition at line 1095 of file core_armv8mml.h.
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
Definition at line 1096 of file core_armv8mml.h.
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
Definition at line 1098 of file core_armv8mml.h.
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
Definition at line 1099 of file core_armv8mml.h.
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
Definition at line 1101 of file core_armv8mml.h.
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
Definition at line 1102 of file core_armv8mml.h.
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
Definition at line 1197 of file core_armv8mml.h.
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
Definition at line 1198 of file core_armv8mml.h.
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
Definition at line 1200 of file core_armv8mml.h.
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
Definition at line 1201 of file core_armv8mml.h.
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
Definition at line 1203 of file core_armv8mml.h.
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
Definition at line 1204 of file core_armv8mml.h.
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
Definition at line 1206 of file core_armv8mml.h.
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
Definition at line 1207 of file core_armv8mml.h.
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
Definition at line 1209 of file core_armv8mml.h.
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
Definition at line 1210 of file core_armv8mml.h.
| #define DWT_CTRL_CYCDISS_Pos 23U |
DWT CTRL: CYCDISS Position
Definition at line 1212 of file core_armv8mml.h.
| #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) |
DWT CTRL: CYCDISS Mask
Definition at line 1213 of file core_armv8mml.h.
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
Definition at line 1215 of file core_armv8mml.h.
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
Definition at line 1216 of file core_armv8mml.h.
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
Definition at line 1218 of file core_armv8mml.h.
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
Definition at line 1219 of file core_armv8mml.h.
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
Definition at line 1221 of file core_armv8mml.h.
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
Definition at line 1222 of file core_armv8mml.h.
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
Definition at line 1224 of file core_armv8mml.h.
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
Definition at line 1225 of file core_armv8mml.h.
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
Definition at line 1227 of file core_armv8mml.h.
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
Definition at line 1228 of file core_armv8mml.h.
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
Definition at line 1230 of file core_armv8mml.h.
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
Definition at line 1231 of file core_armv8mml.h.
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
Definition at line 1233 of file core_armv8mml.h.
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
Definition at line 1234 of file core_armv8mml.h.
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
Definition at line 1236 of file core_armv8mml.h.
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
Definition at line 1237 of file core_armv8mml.h.
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
Definition at line 1239 of file core_armv8mml.h.
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
Definition at line 1240 of file core_armv8mml.h.
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
Definition at line 1242 of file core_armv8mml.h.
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
Definition at line 1243 of file core_armv8mml.h.
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
Definition at line 1245 of file core_armv8mml.h.
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
Definition at line 1246 of file core_armv8mml.h.
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
Definition at line 1248 of file core_armv8mml.h.
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
Definition at line 1249 of file core_armv8mml.h.
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
Definition at line 1251 of file core_armv8mml.h.
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
Definition at line 1252 of file core_armv8mml.h.
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
Definition at line 1255 of file core_armv8mml.h.
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
Definition at line 1256 of file core_armv8mml.h.
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
Definition at line 1259 of file core_armv8mml.h.
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
Definition at line 1260 of file core_armv8mml.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
Definition at line 1263 of file core_armv8mml.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
Definition at line 1264 of file core_armv8mml.h.
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
Definition at line 1267 of file core_armv8mml.h.
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
Definition at line 1268 of file core_armv8mml.h.
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
Definition at line 1271 of file core_armv8mml.h.
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
Definition at line 1272 of file core_armv8mml.h.
| #define DWT_FUNCTION_ID_Pos 27U |
DWT FUNCTION: ID Position
Definition at line 1275 of file core_armv8mml.h.
| #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) |
DWT FUNCTION: ID Mask
Definition at line 1276 of file core_armv8mml.h.
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
Definition at line 1278 of file core_armv8mml.h.
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
Definition at line 1279 of file core_armv8mml.h.
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
Definition at line 1281 of file core_armv8mml.h.
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
Definition at line 1282 of file core_armv8mml.h.
| #define DWT_FUNCTION_ACTION_Pos 4U |
DWT FUNCTION: ACTION Position
Definition at line 1284 of file core_armv8mml.h.
| #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) |
DWT FUNCTION: ACTION Mask
Definition at line 1285 of file core_armv8mml.h.
| #define DWT_FUNCTION_MATCH_Pos 0U |
DWT FUNCTION: MATCH Position
Definition at line 1287 of file core_armv8mml.h.
| #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) |
DWT FUNCTION: MATCH Mask
Definition at line 1288 of file core_armv8mml.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 1328 of file core_armv8mml.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 1329 of file core_armv8mml.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 1332 of file core_armv8mml.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 1333 of file core_armv8mml.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 1335 of file core_armv8mml.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 1336 of file core_armv8mml.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 1338 of file core_armv8mml.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 1339 of file core_armv8mml.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 1341 of file core_armv8mml.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 1342 of file core_armv8mml.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 1345 of file core_armv8mml.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 1346 of file core_armv8mml.h.
| #define TPI_FFCR_FOnMan_Pos 6U |
TPI FFCR: FOnMan Position
Definition at line 1348 of file core_armv8mml.h.
| #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) |
TPI FFCR: FOnMan Mask
Definition at line 1349 of file core_armv8mml.h.
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
Definition at line 1351 of file core_armv8mml.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 1352 of file core_armv8mml.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 1369 of file core_armv8mml.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1370 of file core_armv8mml.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 1372 of file core_armv8mml.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1373 of file core_armv8mml.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 1375 of file core_armv8mml.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1376 of file core_armv8mml.h.
| #define TPI_DEVID_FIFOSZ_Pos 6U |
TPI DEVID: FIFO depth Position
TPI DEVID: FIFOSZ Position
Definition at line 1378 of file core_armv8mml.h.
| #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) |
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
Definition at line 1382 of file core_armv8mml.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 1383 of file core_armv8mml.h.
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
Definition at line 1385 of file core_armv8mml.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1386 of file core_armv8mml.h.
| #define MPU_TYPE_IREGION_Pos 16U |
MPU TYPE: IREGION Position
Definition at line 1428 of file core_armv8mml.h.
| #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) |
MPU TYPE: IREGION Mask
Definition at line 1429 of file core_armv8mml.h.
| #define MPU_TYPE_DREGION_Pos 8U |
MPU TYPE: DREGION Position
Definition at line 1431 of file core_armv8mml.h.
| #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) |
MPU TYPE: DREGION Mask
Definition at line 1432 of file core_armv8mml.h.
| #define MPU_TYPE_SEPARATE_Pos 0U |
MPU TYPE: SEPARATE Position
Definition at line 1434 of file core_armv8mml.h.
| #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) |
MPU TYPE: SEPARATE Mask
Definition at line 1435 of file core_armv8mml.h.
| #define MPU_CTRL_PRIVDEFENA_Pos 2U |
MPU CTRL: PRIVDEFENA Position
Definition at line 1438 of file core_armv8mml.h.
| #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) |
MPU CTRL: PRIVDEFENA Mask
Definition at line 1439 of file core_armv8mml.h.
| #define MPU_CTRL_HFNMIENA_Pos 1U |
MPU CTRL: HFNMIENA Position
Definition at line 1441 of file core_armv8mml.h.
| #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) |
MPU CTRL: HFNMIENA Mask
Definition at line 1442 of file core_armv8mml.h.
| #define MPU_CTRL_ENABLE_Pos 0U |
MPU CTRL: ENABLE Position
Definition at line 1444 of file core_armv8mml.h.
| #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) |
MPU CTRL: ENABLE Mask
Definition at line 1445 of file core_armv8mml.h.
| #define MPU_RNR_REGION_Pos 0U |
MPU RNR: REGION Position
Definition at line 1448 of file core_armv8mml.h.
| #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) |
MPU RNR: REGION Mask
Definition at line 1449 of file core_armv8mml.h.
| #define MPU_RBAR_BASE_Pos 5U |
MPU RBAR: BASE Position
Definition at line 1452 of file core_armv8mml.h.
| #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) |
MPU RBAR: BASE Mask
Definition at line 1453 of file core_armv8mml.h.
| #define MPU_RBAR_SH_Pos 3U |
MPU RBAR: SH Position
Definition at line 1455 of file core_armv8mml.h.
| #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) |
MPU RBAR: SH Mask
Definition at line 1456 of file core_armv8mml.h.
| #define MPU_RBAR_AP_Pos 1U |
MPU RBAR: AP Position
Definition at line 1458 of file core_armv8mml.h.
| #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) |
MPU RBAR: AP Mask
Definition at line 1459 of file core_armv8mml.h.
| #define MPU_RBAR_XN_Pos 0U |
MPU RBAR: XN Position
Definition at line 1461 of file core_armv8mml.h.
| #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) |
MPU RBAR: XN Mask
Definition at line 1462 of file core_armv8mml.h.
| #define MPU_RLAR_LIMIT_Pos 5U |
MPU RLAR: LIMIT Position
Definition at line 1465 of file core_armv8mml.h.
| #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) |
MPU RLAR: LIMIT Mask
Definition at line 1466 of file core_armv8mml.h.
| #define MPU_RLAR_AttrIndx_Pos 1U |
MPU RLAR: AttrIndx Position
Definition at line 1468 of file core_armv8mml.h.
| #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) |
MPU RLAR: AttrIndx Mask
Definition at line 1469 of file core_armv8mml.h.
| #define MPU_RLAR_EN_Pos 0U |
MPU RLAR: Region enable bit Position
MPU RLAR: EN Position
Definition at line 1471 of file core_armv8mml.h.
| #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) |
MPU RLAR: Region enable bit Disable Mask
MPU RLAR: EN Mask
Definition at line 1472 of file core_armv8mml.h.
| #define MPU_MAIR0_Attr3_Pos 24U |
MPU MAIR0: Attr3 Position
Definition at line 1475 of file core_armv8mml.h.
| #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) |
MPU MAIR0: Attr3 Mask
Definition at line 1476 of file core_armv8mml.h.
| #define MPU_MAIR0_Attr2_Pos 16U |
MPU MAIR0: Attr2 Position
Definition at line 1478 of file core_armv8mml.h.
| #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) |
MPU MAIR0: Attr2 Mask
Definition at line 1479 of file core_armv8mml.h.
| #define MPU_MAIR0_Attr1_Pos 8U |
MPU MAIR0: Attr1 Position
Definition at line 1481 of file core_armv8mml.h.
| #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) |
MPU MAIR0: Attr1 Mask
Definition at line 1482 of file core_armv8mml.h.
| #define MPU_MAIR0_Attr0_Pos 0U |
MPU MAIR0: Attr0 Position
Definition at line 1484 of file core_armv8mml.h.
| #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) |
MPU MAIR0: Attr0 Mask
Definition at line 1485 of file core_armv8mml.h.
| #define MPU_MAIR1_Attr7_Pos 24U |
MPU MAIR1: Attr7 Position
Definition at line 1488 of file core_armv8mml.h.
| #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) |
MPU MAIR1: Attr7 Mask
Definition at line 1489 of file core_armv8mml.h.
| #define MPU_MAIR1_Attr6_Pos 16U |
MPU MAIR1: Attr6 Position
Definition at line 1491 of file core_armv8mml.h.
| #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) |
MPU MAIR1: Attr6 Mask
Definition at line 1492 of file core_armv8mml.h.
| #define MPU_MAIR1_Attr5_Pos 8U |
MPU MAIR1: Attr5 Position
Definition at line 1494 of file core_armv8mml.h.
| #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) |
MPU MAIR1: Attr5 Mask
Definition at line 1495 of file core_armv8mml.h.
| #define MPU_MAIR1_Attr4_Pos 0U |
MPU MAIR1: Attr4 Position
Definition at line 1497 of file core_armv8mml.h.
| #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) |
MPU MAIR1: Attr4 Mask
Definition at line 1498 of file core_armv8mml.h.
| #define FPU_FPCCR_ASPEN_Pos 31U |
FPCCR: ASPEN bit Position
Definition at line 1613 of file core_armv8mml.h.
| #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) |
FPCCR: ASPEN bit Mask
Definition at line 1614 of file core_armv8mml.h.
| #define FPU_FPCCR_LSPEN_Pos 30U |
FPCCR: LSPEN Position
Definition at line 1616 of file core_armv8mml.h.
| #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) |
FPCCR: LSPEN bit Mask
Definition at line 1617 of file core_armv8mml.h.
| #define FPU_FPCCR_LSPENS_Pos 29U |
FPCCR: LSPENS Position
Definition at line 1619 of file core_armv8mml.h.
| #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) |
FPCCR: LSPENS bit Mask
Definition at line 1620 of file core_armv8mml.h.
| #define FPU_FPCCR_CLRONRET_Pos 28U |
FPCCR: CLRONRET Position
Definition at line 1622 of file core_armv8mml.h.
| #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) |
FPCCR: CLRONRET bit Mask
Definition at line 1623 of file core_armv8mml.h.
| #define FPU_FPCCR_CLRONRETS_Pos 27U |
FPCCR: CLRONRETS Position
Definition at line 1625 of file core_armv8mml.h.
| #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) |
FPCCR: CLRONRETS bit Mask
Definition at line 1626 of file core_armv8mml.h.
| #define FPU_FPCCR_TS_Pos 26U |
FPCCR: TS Position
Definition at line 1628 of file core_armv8mml.h.
| #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) |
FPCCR: TS bit Mask
Definition at line 1629 of file core_armv8mml.h.
| #define FPU_FPCCR_UFRDY_Pos 10U |
FPCCR: UFRDY Position
Definition at line 1631 of file core_armv8mml.h.
| #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) |
FPCCR: UFRDY bit Mask
Definition at line 1632 of file core_armv8mml.h.
| #define FPU_FPCCR_SPLIMVIOL_Pos 9U |
FPCCR: SPLIMVIOL Position
Definition at line 1634 of file core_armv8mml.h.
| #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) |
FPCCR: SPLIMVIOL bit Mask
Definition at line 1635 of file core_armv8mml.h.
| #define FPU_FPCCR_MONRDY_Pos 8U |
FPCCR: MONRDY Position
Definition at line 1637 of file core_armv8mml.h.
| #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) |
FPCCR: MONRDY bit Mask
Definition at line 1638 of file core_armv8mml.h.
| #define FPU_FPCCR_SFRDY_Pos 7U |
FPCCR: SFRDY Position
Definition at line 1640 of file core_armv8mml.h.
| #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) |
FPCCR: SFRDY bit Mask
Definition at line 1641 of file core_armv8mml.h.
| #define FPU_FPCCR_BFRDY_Pos 6U |
FPCCR: BFRDY Position
Definition at line 1643 of file core_armv8mml.h.
| #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) |
FPCCR: BFRDY bit Mask
Definition at line 1644 of file core_armv8mml.h.
| #define FPU_FPCCR_MMRDY_Pos 5U |
FPCCR: MMRDY Position
Definition at line 1646 of file core_armv8mml.h.
| #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) |
FPCCR: MMRDY bit Mask
Definition at line 1647 of file core_armv8mml.h.
| #define FPU_FPCCR_HFRDY_Pos 4U |
FPCCR: HFRDY Position
Definition at line 1649 of file core_armv8mml.h.
| #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) |
FPCCR: HFRDY bit Mask
Definition at line 1650 of file core_armv8mml.h.
| #define FPU_FPCCR_THREAD_Pos 3U |
FPCCR: processor mode bit Position
Definition at line 1652 of file core_armv8mml.h.
| #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) |
FPCCR: processor mode active bit Mask
Definition at line 1653 of file core_armv8mml.h.
| #define FPU_FPCCR_S_Pos 2U |
FPCCR: Security status of the FP context bit Position
Definition at line 1655 of file core_armv8mml.h.
| #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) |
FPCCR: Security status of the FP context bit Mask
Definition at line 1656 of file core_armv8mml.h.
| #define FPU_FPCCR_USER_Pos 1U |
FPCCR: privilege level bit Position
Definition at line 1658 of file core_armv8mml.h.
| #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) |
FPCCR: privilege level bit Mask
Definition at line 1659 of file core_armv8mml.h.
| #define FPU_FPCCR_LSPACT_Pos 0U |
FPCCR: Lazy state preservation active bit Position
Definition at line 1661 of file core_armv8mml.h.
| #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) |
FPCCR: Lazy state preservation active bit Mask
Definition at line 1662 of file core_armv8mml.h.
| #define FPU_FPCAR_ADDRESS_Pos 3U |
FPCAR: ADDRESS bit Position
Definition at line 1665 of file core_armv8mml.h.
| #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) |
FPCAR: ADDRESS bit Mask
Definition at line 1666 of file core_armv8mml.h.
| #define FPU_FPDSCR_AHP_Pos 26U |
FPDSCR: AHP bit Position
Definition at line 1669 of file core_armv8mml.h.
| #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) |
FPDSCR: AHP bit Mask
Definition at line 1670 of file core_armv8mml.h.
| #define FPU_FPDSCR_DN_Pos 25U |
FPDSCR: DN bit Position
Definition at line 1672 of file core_armv8mml.h.
| #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) |
FPDSCR: DN bit Mask
Definition at line 1673 of file core_armv8mml.h.
| #define FPU_FPDSCR_FZ_Pos 24U |
FPDSCR: FZ bit Position
Definition at line 1675 of file core_armv8mml.h.
| #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) |
FPDSCR: FZ bit Mask
Definition at line 1676 of file core_armv8mml.h.
| #define FPU_FPDSCR_RMode_Pos 22U |
FPDSCR: RMode bit Position
Definition at line 1678 of file core_armv8mml.h.
| #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) |
FPDSCR: RMode bit Mask
Definition at line 1679 of file core_armv8mml.h.
| #define FPU_MVFR0_FP_rounding_modes_Pos 28U |
MVFR0: FP rounding modes bits Position
Definition at line 1682 of file core_armv8mml.h.
| #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) |
MVFR0: FP rounding modes bits Mask
Definition at line 1683 of file core_armv8mml.h.
| #define FPU_MVFR0_Short_vectors_Pos 24U |
MVFR0: Short vectors bits Position
Definition at line 1685 of file core_armv8mml.h.
| #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) |
MVFR0: Short vectors bits Mask
Definition at line 1686 of file core_armv8mml.h.
| #define FPU_MVFR0_Square_root_Pos 20U |
MVFR0: Square root bits Position
Definition at line 1688 of file core_armv8mml.h.
| #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) |
MVFR0: Square root bits Mask
Definition at line 1689 of file core_armv8mml.h.
| #define FPU_MVFR0_Divide_Pos 16U |
MVFR0: Divide bits Position
Definition at line 1691 of file core_armv8mml.h.
| #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) |
MVFR0: Divide bits Mask
Definition at line 1692 of file core_armv8mml.h.
| #define FPU_MVFR0_FP_excep_trapping_Pos 12U |
MVFR0: FP exception trapping bits Position
Definition at line 1694 of file core_armv8mml.h.
| #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) |
MVFR0: FP exception trapping bits Mask
Definition at line 1695 of file core_armv8mml.h.
| #define FPU_MVFR0_Double_precision_Pos 8U |
MVFR0: Double-precision bits Position
Definition at line 1697 of file core_armv8mml.h.
| #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) |
MVFR0: Double-precision bits Mask
Definition at line 1698 of file core_armv8mml.h.
| #define FPU_MVFR0_Single_precision_Pos 4U |
MVFR0: Single-precision bits Position
Definition at line 1700 of file core_armv8mml.h.
| #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) |
MVFR0: Single-precision bits Mask
Definition at line 1701 of file core_armv8mml.h.
| #define FPU_MVFR0_A_SIMD_registers_Pos 0U |
MVFR0: A_SIMD registers bits Position
Definition at line 1703 of file core_armv8mml.h.
| #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) |
MVFR0: A_SIMD registers bits Mask
Definition at line 1704 of file core_armv8mml.h.
| #define FPU_MVFR1_FP_fused_MAC_Pos 28U |
MVFR1: FP fused MAC bits Position
Definition at line 1707 of file core_armv8mml.h.
| #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) |
MVFR1: FP fused MAC bits Mask
Definition at line 1708 of file core_armv8mml.h.
| #define FPU_MVFR1_FP_HPFP_Pos 24U |
MVFR1: FP HPFP bits Position
Definition at line 1710 of file core_armv8mml.h.
| #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) |
MVFR1: FP HPFP bits Mask
Definition at line 1711 of file core_armv8mml.h.
| #define FPU_MVFR1_D_NaN_mode_Pos 4U |
MVFR1: D_NaN mode bits Position
Definition at line 1713 of file core_armv8mml.h.
| #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) |
MVFR1: D_NaN mode bits Mask
Definition at line 1714 of file core_armv8mml.h.
| #define FPU_MVFR1_FtZ_mode_Pos 0U |
MVFR1: FtZ mode bits Position
Definition at line 1716 of file core_armv8mml.h.
| #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) |
MVFR1: FtZ mode bits Mask
Definition at line 1717 of file core_armv8mml.h.
| #define FPU_MVFR2_FPMisc_Pos 4U |
MVFR2: FPMisc bits Position
Definition at line 1720 of file core_armv8mml.h.
| #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) |
MVFR2: FPMisc bits Mask
Definition at line 1721 of file core_armv8mml.h.
| #define DCB_DHCSR_DBGKEY_Pos 16U |
DCB DHCSR: Debug key Position
Definition at line 1882 of file core_armv8mml.h.
| #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) |
DCB DHCSR: Debug key Mask
Definition at line 1883 of file core_armv8mml.h.
| #define DCB_DHCSR_S_RESTART_ST_Pos 26U |
DCB DHCSR: Restart sticky status Position
Definition at line 1885 of file core_armv8mml.h.
| #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) |
DCB DHCSR: Restart sticky status Mask
Definition at line 1886 of file core_armv8mml.h.
| #define DCB_DHCSR_S_RESET_ST_Pos 25U |
DCB DHCSR: Reset sticky status Position
Definition at line 1888 of file core_armv8mml.h.
| #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) |
DCB DHCSR: Reset sticky status Mask
Definition at line 1889 of file core_armv8mml.h.
| #define DCB_DHCSR_S_RETIRE_ST_Pos 24U |
DCB DHCSR: Retire sticky status Position
Definition at line 1891 of file core_armv8mml.h.
| #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) |
DCB DHCSR: Retire sticky status Mask
Definition at line 1892 of file core_armv8mml.h.
| #define DCB_DHCSR_S_SDE_Pos 20U |
DCB DHCSR: Secure debug enabled Position
Definition at line 1894 of file core_armv8mml.h.
| #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) |
DCB DHCSR: Secure debug enabled Mask
Definition at line 1895 of file core_armv8mml.h.
| #define DCB_DHCSR_S_LOCKUP_Pos 19U |
DCB DHCSR: Lockup status Position
Definition at line 1897 of file core_armv8mml.h.
| #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) |
DCB DHCSR: Lockup status Mask
Definition at line 1898 of file core_armv8mml.h.
| #define DCB_DHCSR_S_SLEEP_Pos 18U |
DCB DHCSR: Sleeping status Position
Definition at line 1900 of file core_armv8mml.h.
| #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) |
DCB DHCSR: Sleeping status Mask
Definition at line 1901 of file core_armv8mml.h.
| #define DCB_DHCSR_S_HALT_Pos 17U |
DCB DHCSR: Halted status Position
Definition at line 1903 of file core_armv8mml.h.
| #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) |
DCB DHCSR: Halted status Mask
Definition at line 1904 of file core_armv8mml.h.
| #define DCB_DHCSR_S_REGRDY_Pos 16U |
DCB DHCSR: Register ready status Position
Definition at line 1906 of file core_armv8mml.h.
| #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) |
DCB DHCSR: Register ready status Mask
Definition at line 1907 of file core_armv8mml.h.
| #define DCB_DHCSR_C_SNAPSTALL_Pos 5U |
DCB DHCSR: Snap stall control Position
Definition at line 1909 of file core_armv8mml.h.
| #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) |
DCB DHCSR: Snap stall control Mask
Definition at line 1910 of file core_armv8mml.h.
| #define DCB_DHCSR_C_MASKINTS_Pos 3U |
DCB DHCSR: Mask interrupts control Position
Definition at line 1912 of file core_armv8mml.h.
| #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) |
DCB DHCSR: Mask interrupts control Mask
Definition at line 1913 of file core_armv8mml.h.
| #define DCB_DHCSR_C_STEP_Pos 2U |
DCB DHCSR: Step control Position
Definition at line 1915 of file core_armv8mml.h.
| #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) |
DCB DHCSR: Step control Mask
Definition at line 1916 of file core_armv8mml.h.
| #define DCB_DHCSR_C_HALT_Pos 1U |
DCB DHCSR: Halt control Position
Definition at line 1918 of file core_armv8mml.h.
| #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) |
DCB DHCSR: Halt control Mask
Definition at line 1919 of file core_armv8mml.h.
| #define DCB_DHCSR_C_DEBUGEN_Pos 0U |
DCB DHCSR: Debug enable control Position
Definition at line 1921 of file core_armv8mml.h.
| #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) |
DCB DHCSR: Debug enable control Mask
Definition at line 1922 of file core_armv8mml.h.
| #define DCB_DCRSR_REGWnR_Pos 16U |
DCB DCRSR: Register write/not-read Position
Definition at line 1925 of file core_armv8mml.h.
| #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) |
DCB DCRSR: Register write/not-read Mask
Definition at line 1926 of file core_armv8mml.h.
| #define DCB_DCRSR_REGSEL_Pos 0U |
DCB DCRSR: Register selector Position
Definition at line 1928 of file core_armv8mml.h.
| #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) |
DCB DCRSR: Register selector Mask
Definition at line 1929 of file core_armv8mml.h.
| #define DCB_DCRDR_DBGTMP_Pos 0U |
DCB DCRDR: Data temporary buffer Position
Definition at line 1932 of file core_armv8mml.h.
| #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) |
DCB DCRDR: Data temporary buffer Mask
Definition at line 1933 of file core_armv8mml.h.
| #define DCB_DEMCR_TRCENA_Pos 24U |
DCB DEMCR: Trace enable Position
Definition at line 1936 of file core_armv8mml.h.
| #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) |
DCB DEMCR: Trace enable Mask
Definition at line 1937 of file core_armv8mml.h.
| #define DCB_DEMCR_MONPRKEY_Pos 23U |
DCB DEMCR: Monitor pend req key Position
Definition at line 1939 of file core_armv8mml.h.
| #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) |
DCB DEMCR: Monitor pend req key Mask
Definition at line 1940 of file core_armv8mml.h.
| #define DCB_DEMCR_UMON_EN_Pos 21U |
DCB DEMCR: Unprivileged monitor enable Position
Definition at line 1942 of file core_armv8mml.h.
| #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) |
DCB DEMCR: Unprivileged monitor enable Mask
Definition at line 1943 of file core_armv8mml.h.
| #define DCB_DEMCR_SDME_Pos 20U |
DCB DEMCR: Secure DebugMonitor enable Position
Definition at line 1945 of file core_armv8mml.h.
| #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) |
DCB DEMCR: Secure DebugMonitor enable Mask
Definition at line 1946 of file core_armv8mml.h.
| #define DCB_DEMCR_MON_REQ_Pos 19U |
DCB DEMCR: Monitor request Position
Definition at line 1948 of file core_armv8mml.h.
| #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) |
DCB DEMCR: Monitor request Mask
Definition at line 1949 of file core_armv8mml.h.
| #define DCB_DEMCR_MON_STEP_Pos 18U |
DCB DEMCR: Monitor step Position
Definition at line 1951 of file core_armv8mml.h.
| #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) |
DCB DEMCR: Monitor step Mask
Definition at line 1952 of file core_armv8mml.h.
| #define DCB_DEMCR_MON_PEND_Pos 17U |
DCB DEMCR: Monitor pend Position
Definition at line 1954 of file core_armv8mml.h.
| #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) |
DCB DEMCR: Monitor pend Mask
Definition at line 1955 of file core_armv8mml.h.
| #define DCB_DEMCR_MON_EN_Pos 16U |
DCB DEMCR: Monitor enable Position
Definition at line 1957 of file core_armv8mml.h.
| #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) |
DCB DEMCR: Monitor enable Mask
Definition at line 1958 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_SFERR_Pos 11U |
DCB DEMCR: Vector Catch SecureFault Position
Definition at line 1960 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) |
DCB DEMCR: Vector Catch SecureFault Mask
Definition at line 1961 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_HARDERR_Pos 10U |
DCB DEMCR: Vector Catch HardFault errors Position
Definition at line 1963 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) |
DCB DEMCR: Vector Catch HardFault errors Mask
Definition at line 1964 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_INTERR_Pos 9U |
DCB DEMCR: Vector Catch interrupt errors Position
Definition at line 1966 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) |
DCB DEMCR: Vector Catch interrupt errors Mask
Definition at line 1967 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_BUSERR_Pos 8U |
DCB DEMCR: Vector Catch BusFault errors Position
Definition at line 1969 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) |
DCB DEMCR: Vector Catch BusFault errors Mask
Definition at line 1970 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_STATERR_Pos 7U |
DCB DEMCR: Vector Catch state errors Position
Definition at line 1972 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) |
DCB DEMCR: Vector Catch state errors Mask
Definition at line 1973 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_CHKERR_Pos 6U |
DCB DEMCR: Vector Catch check errors Position
Definition at line 1975 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) |
DCB DEMCR: Vector Catch check errors Mask
Definition at line 1976 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_NOCPERR_Pos 5U |
DCB DEMCR: Vector Catch NOCP errors Position
Definition at line 1978 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) |
DCB DEMCR: Vector Catch NOCP errors Mask
Definition at line 1979 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_MMERR_Pos 4U |
DCB DEMCR: Vector Catch MemManage errors Position
Definition at line 1981 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) |
DCB DEMCR: Vector Catch MemManage errors Mask
Definition at line 1982 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_CORERESET_Pos 0U |
DCB DEMCR: Vector Catch Core reset Position
Definition at line 1984 of file core_armv8mml.h.
| #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) |
DCB DEMCR: Vector Catch Core reset Mask
Definition at line 1985 of file core_armv8mml.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position
Definition at line 1988 of file core_armv8mml.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask
Definition at line 1989 of file core_armv8mml.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U |
DCB DAUTHCTRL: Secure non-invasive debug enable select Position
Definition at line 1991 of file core_armv8mml.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) |
DCB DAUTHCTRL: Secure non-invasive debug enable select Mask
Definition at line 1992 of file core_armv8mml.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U |
DCB DAUTHCTRL: Internal Secure invasive debug enable Position
Definition at line 1994 of file core_armv8mml.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure invasive debug enable Mask
Definition at line 1995 of file core_armv8mml.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U |
DCB DAUTHCTRL: Secure invasive debug enable select Position
Definition at line 1997 of file core_armv8mml.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) |
DCB DAUTHCTRL: Secure invasive debug enable select Mask
Definition at line 1998 of file core_armv8mml.h.
| #define DCB_DSCSR_CDSKEY_Pos 17U |
DCB DSCSR: CDS write-enable key Position
Definition at line 2001 of file core_armv8mml.h.
| #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) |
DCB DSCSR: CDS write-enable key Mask
Definition at line 2002 of file core_armv8mml.h.
| #define DCB_DSCSR_CDS_Pos 16U |
DCB DSCSR: Current domain Secure Position
Definition at line 2004 of file core_armv8mml.h.
| #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) |
DCB DSCSR: Current domain Secure Mask
Definition at line 2005 of file core_armv8mml.h.
| #define DCB_DSCSR_SBRSEL_Pos 1U |
DCB DSCSR: Secure banked register select Position
Definition at line 2007 of file core_armv8mml.h.
| #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) |
DCB DSCSR: Secure banked register select Mask
Definition at line 2008 of file core_armv8mml.h.
| #define DCB_DSCSR_SBRSELEN_Pos 0U |
DCB DSCSR: Secure banked register select enable Position
Definition at line 2010 of file core_armv8mml.h.
| #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) |
DCB DSCSR: Secure banked register select enable Mask
Definition at line 2011 of file core_armv8mml.h.
| #define DIB_DLAR_KEY_Pos 0U |
DIB DLAR: KEY Position
Definition at line 2037 of file core_armv8mml.h.
| #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) |
DIB DLAR: KEY Mask
Definition at line 2038 of file core_armv8mml.h.
| #define DIB_DLSR_nTT_Pos 2U |
DIB DLSR: Not thirty-two bit Position
Definition at line 2041 of file core_armv8mml.h.
| #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) |
DIB DLSR: Not thirty-two bit Mask
Definition at line 2042 of file core_armv8mml.h.
| #define DIB_DLSR_SLK_Pos 1U |
DIB DLSR: Software Lock status Position
Definition at line 2044 of file core_armv8mml.h.
| #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) |
DIB DLSR: Software Lock status Mask
Definition at line 2045 of file core_armv8mml.h.
| #define DIB_DLSR_SLI_Pos 0U |
DIB DLSR: Software Lock implemented Position
Definition at line 2047 of file core_armv8mml.h.
| #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) |
DIB DLSR: Software Lock implemented Mask
Definition at line 2048 of file core_armv8mml.h.
| #define DIB_DAUTHSTATUS_SNID_Pos 6U |
DIB DAUTHSTATUS: Secure Non-invasive Debug Position
Definition at line 2051 of file core_armv8mml.h.
| #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) |
DIB DAUTHSTATUS: Secure Non-invasive Debug Mask
Definition at line 2052 of file core_armv8mml.h.
| #define DIB_DAUTHSTATUS_SID_Pos 4U |
DIB DAUTHSTATUS: Secure Invasive Debug Position
Definition at line 2054 of file core_armv8mml.h.
| #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) |
DIB DAUTHSTATUS: Secure Invasive Debug Mask
Definition at line 2055 of file core_armv8mml.h.
| #define DIB_DAUTHSTATUS_NSNID_Pos 2U |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position
Definition at line 2057 of file core_armv8mml.h.
| #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask
Definition at line 2058 of file core_armv8mml.h.
| #define DIB_DAUTHSTATUS_NSID_Pos 0U |
DIB DAUTHSTATUS: Non-secure Invasive Debug Position
Definition at line 2060 of file core_armv8mml.h.
| #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) |
DIB DAUTHSTATUS: Non-secure Invasive Debug Mask
Definition at line 2061 of file core_armv8mml.h.
| #define DIB_DDEVARCH_ARCHITECT_Pos 21U |
DIB DDEVARCH: Architect Position
Definition at line 2064 of file core_armv8mml.h.
| #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) |
DIB DDEVARCH: Architect Mask
Definition at line 2065 of file core_armv8mml.h.
| #define DIB_DDEVARCH_PRESENT_Pos 20U |
DIB DDEVARCH: DEVARCH Present Position
Definition at line 2067 of file core_armv8mml.h.
| #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) |
DIB DDEVARCH: DEVARCH Present Mask
Definition at line 2068 of file core_armv8mml.h.
| #define DIB_DDEVARCH_REVISION_Pos 16U |
DIB DDEVARCH: Revision Position
Definition at line 2070 of file core_armv8mml.h.
| #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) |
DIB DDEVARCH: Revision Mask
Definition at line 2071 of file core_armv8mml.h.
| #define DIB_DDEVARCH_ARCHVER_Pos 12U |
DIB DDEVARCH: Architecture Version Position
Definition at line 2073 of file core_armv8mml.h.
| #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) |
DIB DDEVARCH: Architecture Version Mask
Definition at line 2074 of file core_armv8mml.h.
| #define DIB_DDEVARCH_ARCHPART_Pos 0U |
DIB DDEVARCH: Architecture Part Position
Definition at line 2076 of file core_armv8mml.h.
| #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) |
DIB DDEVARCH: Architecture Part Mask
Definition at line 2077 of file core_armv8mml.h.
| #define DIB_DDEVTYPE_SUB_Pos 4U |
DIB DDEVTYPE: Sub-type Position
Definition at line 2080 of file core_armv8mml.h.
| #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) |
DIB DDEVTYPE: Sub-type Mask
Definition at line 2081 of file core_armv8mml.h.
| #define DIB_DDEVTYPE_MAJOR_Pos 0U |
DIB DDEVTYPE: Major type Position
Definition at line 2083 of file core_armv8mml.h.
| #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) |
DIB DDEVTYPE: Major type Mask
Definition at line 2084 of file core_armv8mml.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 2103 of file core_armv8mml.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 2111 of file core_armv8mml.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 2124 of file core_armv8mml.h.
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
Definition at line 2125 of file core_armv8mml.h.
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
Definition at line 2126 of file core_armv8mml.h.
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
Definition at line 2127 of file core_armv8mml.h.
| #define DCB_BASE (0xE000EDF0UL) |
DCB Base Address
Definition at line 2129 of file core_armv8mml.h.
| #define DIB_BASE (0xE000EFB0UL) |
DIB Base Address
Definition at line 2130 of file core_armv8mml.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 2131 of file core_armv8mml.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 2132 of file core_armv8mml.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 2133 of file core_armv8mml.h.
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
Definition at line 2135 of file core_armv8mml.h.
SCB configuration struct
Definition at line 2136 of file core_armv8mml.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 2137 of file core_armv8mml.h.
NVIC configuration struct
Definition at line 2138 of file core_armv8mml.h.
ITM configuration struct
Definition at line 2139 of file core_armv8mml.h.
DWT configuration struct
Definition at line 2140 of file core_armv8mml.h.
TPI configuration struct
Definition at line 2141 of file core_armv8mml.h.
DCB configuration struct
Definition at line 2143 of file core_armv8mml.h.
DIB configuration struct
Definition at line 2144 of file core_armv8mml.h.
| #define MPU_BASE (SCS_BASE + 0x0D90UL) |
Memory Protection Unit
Definition at line 2147 of file core_armv8mml.h.
Memory Protection Unit
Definition at line 2148 of file core_armv8mml.h.
| #define FPU_BASE (SCS_BASE + 0x0F30UL) |
Floating Point Unit
Definition at line 2156 of file core_armv8mml.h.
Floating Point Unit
Definition at line 2157 of file core_armv8mml.h.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 3133 of file core_armv8mml.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 355 of file core_cm0.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 356 of file core_cm0.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 358 of file core_cm0.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 359 of file core_cm0.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 361 of file core_cm0.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 362 of file core_cm0.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 364 of file core_cm0.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 365 of file core_cm0.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 367 of file core_cm0.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 368 of file core_cm0.h.
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
Definition at line 371 of file core_cm0.h.
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
Definition at line 372 of file core_cm0.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 374 of file core_cm0.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 375 of file core_cm0.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 377 of file core_cm0.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 378 of file core_cm0.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 380 of file core_cm0.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 381 of file core_cm0.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 383 of file core_cm0.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 384 of file core_cm0.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 386 of file core_cm0.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 387 of file core_cm0.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 389 of file core_cm0.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 390 of file core_cm0.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 392 of file core_cm0.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 393 of file core_cm0.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 395 of file core_cm0.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 396 of file core_cm0.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 399 of file core_cm0.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 400 of file core_cm0.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 402 of file core_cm0.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 403 of file core_cm0.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 405 of file core_cm0.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 406 of file core_cm0.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 408 of file core_cm0.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 409 of file core_cm0.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 411 of file core_cm0.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 412 of file core_cm0.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 415 of file core_cm0.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 416 of file core_cm0.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 418 of file core_cm0.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 419 of file core_cm0.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 421 of file core_cm0.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 422 of file core_cm0.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 428 of file core_cm0.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 429 of file core_cm0.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 432 of file core_cm0.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 433 of file core_cm0.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 457 of file core_cm0.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 458 of file core_cm0.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 460 of file core_cm0.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 461 of file core_cm0.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 463 of file core_cm0.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 464 of file core_cm0.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 466 of file core_cm0.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 467 of file core_cm0.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 470 of file core_cm0.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 471 of file core_cm0.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 474 of file core_cm0.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 475 of file core_cm0.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 478 of file core_cm0.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 479 of file core_cm0.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 481 of file core_cm0.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 482 of file core_cm0.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 484 of file core_cm0.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 485 of file core_cm0.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 513 of file core_cm0.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 521 of file core_cm0.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 534 of file core_cm0.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 535 of file core_cm0.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 536 of file core_cm0.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 537 of file core_cm0.h.
SCB configuration struct
Definition at line 539 of file core_cm0.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 540 of file core_cm0.h.
NVIC configuration struct
Definition at line 541 of file core_cm0.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 373 of file core_cm0plus.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 374 of file core_cm0plus.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 376 of file core_cm0plus.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 377 of file core_cm0plus.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 379 of file core_cm0plus.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 380 of file core_cm0plus.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 382 of file core_cm0plus.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 383 of file core_cm0plus.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 385 of file core_cm0plus.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 386 of file core_cm0plus.h.
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
Definition at line 389 of file core_cm0plus.h.
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
Definition at line 390 of file core_cm0plus.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 392 of file core_cm0plus.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 393 of file core_cm0plus.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 395 of file core_cm0plus.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 396 of file core_cm0plus.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 398 of file core_cm0plus.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 399 of file core_cm0plus.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 401 of file core_cm0plus.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 402 of file core_cm0plus.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 404 of file core_cm0plus.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 405 of file core_cm0plus.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 407 of file core_cm0plus.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 408 of file core_cm0plus.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 410 of file core_cm0plus.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 411 of file core_cm0plus.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 413 of file core_cm0plus.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 414 of file core_cm0plus.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 423 of file core_cm0plus.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 424 of file core_cm0plus.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 426 of file core_cm0plus.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 427 of file core_cm0plus.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 429 of file core_cm0plus.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 430 of file core_cm0plus.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 432 of file core_cm0plus.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 433 of file core_cm0plus.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 435 of file core_cm0plus.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 436 of file core_cm0plus.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 439 of file core_cm0plus.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 440 of file core_cm0plus.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 442 of file core_cm0plus.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 443 of file core_cm0plus.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 445 of file core_cm0plus.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 446 of file core_cm0plus.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 452 of file core_cm0plus.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 453 of file core_cm0plus.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 456 of file core_cm0plus.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 457 of file core_cm0plus.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 481 of file core_cm0plus.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 482 of file core_cm0plus.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 484 of file core_cm0plus.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 485 of file core_cm0plus.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 487 of file core_cm0plus.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 488 of file core_cm0plus.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 490 of file core_cm0plus.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 491 of file core_cm0plus.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 494 of file core_cm0plus.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 495 of file core_cm0plus.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 498 of file core_cm0plus.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 499 of file core_cm0plus.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 502 of file core_cm0plus.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 503 of file core_cm0plus.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 505 of file core_cm0plus.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 506 of file core_cm0plus.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 508 of file core_cm0plus.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 509 of file core_cm0plus.h.
| #define MPU_TYPE_IREGION_Pos 16U |
MPU TYPE: IREGION Position
Definition at line 536 of file core_cm0plus.h.
| #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) |
MPU TYPE: IREGION Mask
Definition at line 537 of file core_cm0plus.h.
| #define MPU_TYPE_DREGION_Pos 8U |
MPU TYPE: DREGION Position
Definition at line 539 of file core_cm0plus.h.
| #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) |
MPU TYPE: DREGION Mask
Definition at line 540 of file core_cm0plus.h.
| #define MPU_TYPE_SEPARATE_Pos 0U |
MPU TYPE: SEPARATE Position
Definition at line 542 of file core_cm0plus.h.
| #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) |
MPU TYPE: SEPARATE Mask
Definition at line 543 of file core_cm0plus.h.
| #define MPU_CTRL_PRIVDEFENA_Pos 2U |
MPU CTRL: PRIVDEFENA Position
Definition at line 546 of file core_cm0plus.h.
| #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) |
MPU CTRL: PRIVDEFENA Mask
Definition at line 547 of file core_cm0plus.h.
| #define MPU_CTRL_HFNMIENA_Pos 1U |
MPU CTRL: HFNMIENA Position
Definition at line 549 of file core_cm0plus.h.
| #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) |
MPU CTRL: HFNMIENA Mask
Definition at line 550 of file core_cm0plus.h.
| #define MPU_CTRL_ENABLE_Pos 0U |
MPU CTRL: ENABLE Position
Definition at line 552 of file core_cm0plus.h.
| #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) |
MPU CTRL: ENABLE Mask
Definition at line 553 of file core_cm0plus.h.
| #define MPU_RNR_REGION_Pos 0U |
MPU RNR: REGION Position
Definition at line 556 of file core_cm0plus.h.
| #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) |
MPU RNR: REGION Mask
Definition at line 557 of file core_cm0plus.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 627 of file core_cm0plus.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 635 of file core_cm0plus.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 648 of file core_cm0plus.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 649 of file core_cm0plus.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 650 of file core_cm0plus.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 651 of file core_cm0plus.h.
SCB configuration struct
Definition at line 653 of file core_cm0plus.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 654 of file core_cm0plus.h.
NVIC configuration struct
Definition at line 655 of file core_cm0plus.h.
| #define MPU_BASE (SCS_BASE + 0x0D90UL) |
Memory Protection Unit
Definition at line 658 of file core_cm0plus.h.
Memory Protection Unit
Definition at line 659 of file core_cm0plus.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 355 of file core_cm1.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 356 of file core_cm1.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 358 of file core_cm1.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 359 of file core_cm1.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 361 of file core_cm1.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 362 of file core_cm1.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 364 of file core_cm1.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 365 of file core_cm1.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 367 of file core_cm1.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 368 of file core_cm1.h.
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
Definition at line 371 of file core_cm1.h.
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
Definition at line 372 of file core_cm1.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 374 of file core_cm1.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 375 of file core_cm1.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 377 of file core_cm1.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 378 of file core_cm1.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 380 of file core_cm1.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 381 of file core_cm1.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 383 of file core_cm1.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 384 of file core_cm1.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 386 of file core_cm1.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 387 of file core_cm1.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 389 of file core_cm1.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 390 of file core_cm1.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 392 of file core_cm1.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 393 of file core_cm1.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 395 of file core_cm1.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 396 of file core_cm1.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 399 of file core_cm1.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 400 of file core_cm1.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 402 of file core_cm1.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 403 of file core_cm1.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 405 of file core_cm1.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 406 of file core_cm1.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 408 of file core_cm1.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 409 of file core_cm1.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 411 of file core_cm1.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 412 of file core_cm1.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 415 of file core_cm1.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 416 of file core_cm1.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 418 of file core_cm1.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 419 of file core_cm1.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 421 of file core_cm1.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 422 of file core_cm1.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 428 of file core_cm1.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 429 of file core_cm1.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 432 of file core_cm1.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 433 of file core_cm1.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 483 of file core_cm1.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 484 of file core_cm1.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 486 of file core_cm1.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 487 of file core_cm1.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 489 of file core_cm1.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 490 of file core_cm1.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 492 of file core_cm1.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 493 of file core_cm1.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 496 of file core_cm1.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 497 of file core_cm1.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 500 of file core_cm1.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 501 of file core_cm1.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 504 of file core_cm1.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 505 of file core_cm1.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 507 of file core_cm1.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 508 of file core_cm1.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 510 of file core_cm1.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 511 of file core_cm1.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 539 of file core_cm1.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 547 of file core_cm1.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 560 of file core_cm1.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 561 of file core_cm1.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 562 of file core_cm1.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 563 of file core_cm1.h.
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
Definition at line 565 of file core_cm1.h.
SCB configuration struct
Definition at line 566 of file core_cm1.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 567 of file core_cm1.h.
NVIC configuration struct
Definition at line 568 of file core_cm1.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 401 of file core_cm23.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 402 of file core_cm23.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 404 of file core_cm23.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 405 of file core_cm23.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 407 of file core_cm23.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 408 of file core_cm23.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 410 of file core_cm23.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 411 of file core_cm23.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 413 of file core_cm23.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 414 of file core_cm23.h.
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
Definition at line 417 of file core_cm23.h.
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
Definition at line 418 of file core_cm23.h.
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
Definition at line 420 of file core_cm23.h.
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
Definition at line 421 of file core_cm23.h.
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
Definition at line 423 of file core_cm23.h.
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
Definition at line 424 of file core_cm23.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 426 of file core_cm23.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 427 of file core_cm23.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 429 of file core_cm23.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 430 of file core_cm23.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 432 of file core_cm23.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 433 of file core_cm23.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 435 of file core_cm23.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 436 of file core_cm23.h.
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
Definition at line 438 of file core_cm23.h.
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
Definition at line 439 of file core_cm23.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 441 of file core_cm23.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 442 of file core_cm23.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 444 of file core_cm23.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 445 of file core_cm23.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 447 of file core_cm23.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 448 of file core_cm23.h.
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
Definition at line 450 of file core_cm23.h.
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
Definition at line 451 of file core_cm23.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 453 of file core_cm23.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 454 of file core_cm23.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 463 of file core_cm23.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 464 of file core_cm23.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 466 of file core_cm23.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 467 of file core_cm23.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 469 of file core_cm23.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 470 of file core_cm23.h.
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
Definition at line 472 of file core_cm23.h.
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
Definition at line 473 of file core_cm23.h.
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
Definition at line 475 of file core_cm23.h.
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
Definition at line 476 of file core_cm23.h.
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
Definition at line 478 of file core_cm23.h.
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
Definition at line 479 of file core_cm23.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 481 of file core_cm23.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 482 of file core_cm23.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 484 of file core_cm23.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 485 of file core_cm23.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 488 of file core_cm23.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 489 of file core_cm23.h.
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
Definition at line 491 of file core_cm23.h.
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
Definition at line 492 of file core_cm23.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 494 of file core_cm23.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 495 of file core_cm23.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 497 of file core_cm23.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 498 of file core_cm23.h.
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
SCB CCR: Branch prediction enable bit Position
Definition at line 501 of file core_cm23.h.
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
SCB CCR: Branch prediction enable bit Mask
Definition at line 502 of file core_cm23.h.
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
SCB CCR: Instruction cache enable bit Position
Definition at line 504 of file core_cm23.h.
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
SCB CCR: Instruction cache enable bit Mask
Definition at line 505 of file core_cm23.h.
| #define SCB_CCR_DC_Pos 16U |
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
Definition at line 510 of file core_cm23.h.
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
Definition at line 511 of file core_cm23.h.
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
Definition at line 513 of file core_cm23.h.
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
Definition at line 514 of file core_cm23.h.
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
Definition at line 516 of file core_cm23.h.
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
Definition at line 517 of file core_cm23.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 519 of file core_cm23.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 520 of file core_cm23.h.
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
Definition at line 522 of file core_cm23.h.
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
Definition at line 523 of file core_cm23.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
Definition at line 526 of file core_cm23.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
Definition at line 527 of file core_cm23.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 529 of file core_cm23.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 530 of file core_cm23.h.
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
Definition at line 532 of file core_cm23.h.
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
Definition at line 533 of file core_cm23.h.
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
Definition at line 535 of file core_cm23.h.
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
Definition at line 536 of file core_cm23.h.
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
Definition at line 538 of file core_cm23.h.
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
Definition at line 539 of file core_cm23.h.
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
Definition at line 541 of file core_cm23.h.
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
Definition at line 542 of file core_cm23.h.
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
Definition at line 544 of file core_cm23.h.
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
Definition at line 545 of file core_cm23.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 569 of file core_cm23.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 570 of file core_cm23.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 572 of file core_cm23.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 573 of file core_cm23.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 575 of file core_cm23.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 576 of file core_cm23.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 578 of file core_cm23.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 579 of file core_cm23.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 582 of file core_cm23.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 583 of file core_cm23.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 586 of file core_cm23.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 587 of file core_cm23.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 590 of file core_cm23.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 591 of file core_cm23.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 593 of file core_cm23.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 594 of file core_cm23.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 596 of file core_cm23.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 597 of file core_cm23.h.
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
Definition at line 683 of file core_cm23.h.
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
Definition at line 684 of file core_cm23.h.
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
Definition at line 686 of file core_cm23.h.
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
Definition at line 687 of file core_cm23.h.
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
Definition at line 689 of file core_cm23.h.
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
Definition at line 690 of file core_cm23.h.
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
Definition at line 692 of file core_cm23.h.
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
Definition at line 693 of file core_cm23.h.
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
Definition at line 695 of file core_cm23.h.
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
Definition at line 696 of file core_cm23.h.
| #define DWT_FUNCTION_ID_Pos 27U |
DWT FUNCTION: ID Position
Definition at line 699 of file core_cm23.h.
| #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) |
DWT FUNCTION: ID Mask
Definition at line 700 of file core_cm23.h.
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
Definition at line 702 of file core_cm23.h.
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
Definition at line 703 of file core_cm23.h.
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
Definition at line 705 of file core_cm23.h.
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
Definition at line 706 of file core_cm23.h.
| #define DWT_FUNCTION_ACTION_Pos 4U |
DWT FUNCTION: ACTION Position
Definition at line 708 of file core_cm23.h.
| #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) |
DWT FUNCTION: ACTION Mask
Definition at line 709 of file core_cm23.h.
| #define DWT_FUNCTION_MATCH_Pos 0U |
DWT FUNCTION: MATCH Position
Definition at line 711 of file core_cm23.h.
| #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) |
DWT FUNCTION: MATCH Mask
Definition at line 712 of file core_cm23.h.
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
Definition at line 756 of file core_cm23.h.
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
Definition at line 757 of file core_cm23.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 760 of file core_cm23.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 761 of file core_cm23.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 764 of file core_cm23.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 765 of file core_cm23.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 767 of file core_cm23.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 768 of file core_cm23.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 770 of file core_cm23.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 771 of file core_cm23.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 773 of file core_cm23.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 774 of file core_cm23.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 777 of file core_cm23.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 778 of file core_cm23.h.
| #define TPI_FFCR_FOnMan_Pos 6U |
TPI FFCR: FOnMan Position
Definition at line 780 of file core_cm23.h.
| #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) |
TPI FFCR: FOnMan Mask
Definition at line 781 of file core_cm23.h.
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
Definition at line 783 of file core_cm23.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 784 of file core_cm23.h.
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
Definition at line 787 of file core_cm23.h.
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
Definition at line 788 of file core_cm23.h.
| #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U |
TPI ITFTTD0: ATB Interface 2 ATVALIDPosition
Definition at line 791 of file core_cm23.h.
| #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) |
TPI ITFTTD0: ATB Interface 2 ATVALID Mask
Definition at line 792 of file core_cm23.h.
| #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U |
TPI ITFTTD0: ATB Interface 2 byte count Position
Definition at line 794 of file core_cm23.h.
| #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) |
TPI ITFTTD0: ATB Interface 2 byte count Mask
Definition at line 795 of file core_cm23.h.
| #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U |
TPI ITFTTD0: ATB Interface 1 ATVALID Position
Definition at line 797 of file core_cm23.h.
| #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) |
TPI ITFTTD0: ATB Interface 1 ATVALID Mask
Definition at line 798 of file core_cm23.h.
| #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U |
TPI ITFTTD0: ATB Interface 1 byte count Position
Definition at line 800 of file core_cm23.h.
| #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) |
TPI ITFTTD0: ATB Interface 1 byte countt Mask
Definition at line 801 of file core_cm23.h.
| #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U |
TPI ITFTTD0: ATB Interface 1 data2 Position
Definition at line 803 of file core_cm23.h.
| #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) |
TPI ITFTTD0: ATB Interface 1 data2 Mask
Definition at line 804 of file core_cm23.h.
| #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U |
TPI ITFTTD0: ATB Interface 1 data1 Position
Definition at line 806 of file core_cm23.h.
| #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) |
TPI ITFTTD0: ATB Interface 1 data1 Mask
Definition at line 807 of file core_cm23.h.
| #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U |
TPI ITFTTD0: ATB Interface 1 data0 Position
Definition at line 809 of file core_cm23.h.
| #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) |
TPI ITFTTD0: ATB Interface 1 data0 Mask
Definition at line 810 of file core_cm23.h.
| #define TPI_ITATBCTR2_AFVALID2S_Pos 1U |
TPI ITATBCTR2: AFVALID2S Position
Definition at line 813 of file core_cm23.h.
| #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) |
TPI ITATBCTR2: AFVALID2SS Mask
Definition at line 814 of file core_cm23.h.
| #define TPI_ITATBCTR2_AFVALID1S_Pos 1U |
TPI ITATBCTR2: AFVALID1S Position
Definition at line 816 of file core_cm23.h.
| #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) |
TPI ITATBCTR2: AFVALID1SS Mask
Definition at line 817 of file core_cm23.h.
| #define TPI_ITATBCTR2_ATREADY2S_Pos 0U |
TPI ITATBCTR2: ATREADY2S Position
Definition at line 819 of file core_cm23.h.
| #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) |
TPI ITATBCTR2: ATREADY2S Mask
Definition at line 820 of file core_cm23.h.
| #define TPI_ITATBCTR2_ATREADY1S_Pos 0U |
TPI ITATBCTR2: ATREADY1S Position
Definition at line 822 of file core_cm23.h.
| #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) |
TPI ITATBCTR2: ATREADY1S Mask
Definition at line 823 of file core_cm23.h.
| #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U |
TPI ITFTTD1: ATB Interface 2 ATVALID Position
Definition at line 826 of file core_cm23.h.
| #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) |
TPI ITFTTD1: ATB Interface 2 ATVALID Mask
Definition at line 827 of file core_cm23.h.
| #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U |
TPI ITFTTD1: ATB Interface 2 byte count Position
Definition at line 829 of file core_cm23.h.
| #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) |
TPI ITFTTD1: ATB Interface 2 byte count Mask
Definition at line 830 of file core_cm23.h.
| #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U |
TPI ITFTTD1: ATB Interface 1 ATVALID Position
Definition at line 832 of file core_cm23.h.
| #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) |
TPI ITFTTD1: ATB Interface 1 ATVALID Mask
Definition at line 833 of file core_cm23.h.
| #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U |
TPI ITFTTD1: ATB Interface 1 byte count Position
Definition at line 835 of file core_cm23.h.
| #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) |
TPI ITFTTD1: ATB Interface 1 byte countt Mask
Definition at line 836 of file core_cm23.h.
| #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U |
TPI ITFTTD1: ATB Interface 2 data2 Position
Definition at line 838 of file core_cm23.h.
| #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) |
TPI ITFTTD1: ATB Interface 2 data2 Mask
Definition at line 839 of file core_cm23.h.
| #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U |
TPI ITFTTD1: ATB Interface 2 data1 Position
Definition at line 841 of file core_cm23.h.
| #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) |
TPI ITFTTD1: ATB Interface 2 data1 Mask
Definition at line 842 of file core_cm23.h.
| #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U |
TPI ITFTTD1: ATB Interface 2 data0 Position
Definition at line 844 of file core_cm23.h.
| #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) |
TPI ITFTTD1: ATB Interface 2 data0 Mask
Definition at line 845 of file core_cm23.h.
| #define TPI_ITATBCTR0_AFVALID2S_Pos 1U |
TPI ITATBCTR0: AFVALID2S Position
Definition at line 848 of file core_cm23.h.
| #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) |
TPI ITATBCTR0: AFVALID2SS Mask
Definition at line 849 of file core_cm23.h.
| #define TPI_ITATBCTR0_AFVALID1S_Pos 1U |
TPI ITATBCTR0: AFVALID1S Position
Definition at line 851 of file core_cm23.h.
| #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) |
TPI ITATBCTR0: AFVALID1SS Mask
Definition at line 852 of file core_cm23.h.
| #define TPI_ITATBCTR0_ATREADY2S_Pos 0U |
TPI ITATBCTR0: ATREADY2S Position
Definition at line 854 of file core_cm23.h.
| #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) |
TPI ITATBCTR0: ATREADY2S Mask
Definition at line 855 of file core_cm23.h.
| #define TPI_ITATBCTR0_ATREADY1S_Pos 0U |
TPI ITATBCTR0: ATREADY1S Position
Definition at line 857 of file core_cm23.h.
| #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) |
TPI ITATBCTR0: ATREADY1S Mask
Definition at line 858 of file core_cm23.h.
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
Definition at line 861 of file core_cm23.h.
| #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
Definition at line 862 of file core_cm23.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 865 of file core_cm23.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 866 of file core_cm23.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 868 of file core_cm23.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 869 of file core_cm23.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 871 of file core_cm23.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 872 of file core_cm23.h.
| #define TPI_DEVID_FIFOSZ_Pos 6U |
TPI DEVID: FIFOSZ Position
TPI DEVID: FIFO depth Position
Definition at line 874 of file core_cm23.h.
| #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) |
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
Definition at line 877 of file core_cm23.h.
| #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
Definition at line 878 of file core_cm23.h.
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
Definition at line 881 of file core_cm23.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 882 of file core_cm23.h.
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
Definition at line 884 of file core_cm23.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 885 of file core_cm23.h.
| #define MPU_TYPE_IREGION_Pos 16U |
MPU TYPE: IREGION Position
Definition at line 921 of file core_cm23.h.
| #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) |
MPU TYPE: IREGION Mask
Definition at line 922 of file core_cm23.h.
| #define MPU_TYPE_DREGION_Pos 8U |
MPU TYPE: DREGION Position
Definition at line 924 of file core_cm23.h.
| #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) |
MPU TYPE: DREGION Mask
Definition at line 925 of file core_cm23.h.
| #define MPU_TYPE_SEPARATE_Pos 0U |
MPU TYPE: SEPARATE Position
Definition at line 927 of file core_cm23.h.
| #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) |
MPU TYPE: SEPARATE Mask
Definition at line 928 of file core_cm23.h.
| #define MPU_CTRL_PRIVDEFENA_Pos 2U |
MPU CTRL: PRIVDEFENA Position
Definition at line 931 of file core_cm23.h.
| #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) |
MPU CTRL: PRIVDEFENA Mask
Definition at line 932 of file core_cm23.h.
| #define MPU_CTRL_HFNMIENA_Pos 1U |
MPU CTRL: HFNMIENA Position
Definition at line 934 of file core_cm23.h.
| #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) |
MPU CTRL: HFNMIENA Mask
Definition at line 935 of file core_cm23.h.
| #define MPU_CTRL_ENABLE_Pos 0U |
MPU CTRL: ENABLE Position
Definition at line 937 of file core_cm23.h.
| #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) |
MPU CTRL: ENABLE Mask
Definition at line 938 of file core_cm23.h.
| #define MPU_RNR_REGION_Pos 0U |
MPU RNR: REGION Position
Definition at line 941 of file core_cm23.h.
| #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) |
MPU RNR: REGION Mask
Definition at line 942 of file core_cm23.h.
| #define MPU_RBAR_BASE_Pos 5U |
MPU RBAR: BASE Position
Definition at line 945 of file core_cm23.h.
| #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) |
MPU RBAR: BASE Mask
Definition at line 946 of file core_cm23.h.
| #define MPU_RBAR_SH_Pos 3U |
MPU RBAR: SH Position
Definition at line 948 of file core_cm23.h.
| #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) |
MPU RBAR: SH Mask
Definition at line 949 of file core_cm23.h.
| #define MPU_RBAR_AP_Pos 1U |
MPU RBAR: AP Position
Definition at line 951 of file core_cm23.h.
| #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) |
MPU RBAR: AP Mask
Definition at line 952 of file core_cm23.h.
| #define MPU_RBAR_XN_Pos 0U |
MPU RBAR: XN Position
Definition at line 954 of file core_cm23.h.
| #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) |
MPU RBAR: XN Mask
Definition at line 955 of file core_cm23.h.
| #define MPU_RLAR_LIMIT_Pos 5U |
MPU RLAR: LIMIT Position
Definition at line 958 of file core_cm23.h.
| #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) |
MPU RLAR: LIMIT Mask
Definition at line 959 of file core_cm23.h.
| #define MPU_RLAR_AttrIndx_Pos 1U |
MPU RLAR: AttrIndx Position
Definition at line 961 of file core_cm23.h.
| #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) |
MPU RLAR: AttrIndx Mask
Definition at line 962 of file core_cm23.h.
| #define MPU_RLAR_EN_Pos 0U |
MPU RLAR: EN Position
MPU RLAR: Region enable bit Position
Definition at line 964 of file core_cm23.h.
| #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) |
MPU RLAR: EN Mask
MPU RLAR: Region enable bit Disable Mask
Definition at line 965 of file core_cm23.h.
| #define MPU_MAIR0_Attr3_Pos 24U |
MPU MAIR0: Attr3 Position
Definition at line 968 of file core_cm23.h.
| #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) |
MPU MAIR0: Attr3 Mask
Definition at line 969 of file core_cm23.h.
| #define MPU_MAIR0_Attr2_Pos 16U |
MPU MAIR0: Attr2 Position
Definition at line 971 of file core_cm23.h.
| #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) |
MPU MAIR0: Attr2 Mask
Definition at line 972 of file core_cm23.h.
| #define MPU_MAIR0_Attr1_Pos 8U |
MPU MAIR0: Attr1 Position
Definition at line 974 of file core_cm23.h.
| #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) |
MPU MAIR0: Attr1 Mask
Definition at line 975 of file core_cm23.h.
| #define MPU_MAIR0_Attr0_Pos 0U |
MPU MAIR0: Attr0 Position
Definition at line 977 of file core_cm23.h.
| #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) |
MPU MAIR0: Attr0 Mask
Definition at line 978 of file core_cm23.h.
| #define MPU_MAIR1_Attr7_Pos 24U |
MPU MAIR1: Attr7 Position
Definition at line 981 of file core_cm23.h.
| #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) |
MPU MAIR1: Attr7 Mask
Definition at line 982 of file core_cm23.h.
| #define MPU_MAIR1_Attr6_Pos 16U |
MPU MAIR1: Attr6 Position
Definition at line 984 of file core_cm23.h.
| #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) |
MPU MAIR1: Attr6 Mask
Definition at line 985 of file core_cm23.h.
| #define MPU_MAIR1_Attr5_Pos 8U |
MPU MAIR1: Attr5 Position
Definition at line 987 of file core_cm23.h.
| #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) |
MPU MAIR1: Attr5 Mask
Definition at line 988 of file core_cm23.h.
| #define MPU_MAIR1_Attr4_Pos 0U |
MPU MAIR1: Attr4 Position
Definition at line 990 of file core_cm23.h.
| #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) |
MPU MAIR1: Attr4 Mask
Definition at line 991 of file core_cm23.h.
| #define DCB_DHCSR_DBGKEY_Pos 16U |
DCB DHCSR: Debug key Position
Definition at line 1179 of file core_cm23.h.
| #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) |
DCB DHCSR: Debug key Mask
Definition at line 1180 of file core_cm23.h.
| #define DCB_DHCSR_S_RESTART_ST_Pos 26U |
DCB DHCSR: Restart sticky status Position
Definition at line 1182 of file core_cm23.h.
| #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) |
DCB DHCSR: Restart sticky status Mask
Definition at line 1183 of file core_cm23.h.
| #define DCB_DHCSR_S_RESET_ST_Pos 25U |
DCB DHCSR: Reset sticky status Position
Definition at line 1185 of file core_cm23.h.
| #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) |
DCB DHCSR: Reset sticky status Mask
Definition at line 1186 of file core_cm23.h.
| #define DCB_DHCSR_S_RETIRE_ST_Pos 24U |
DCB DHCSR: Retire sticky status Position
Definition at line 1188 of file core_cm23.h.
| #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) |
DCB DHCSR: Retire sticky status Mask
Definition at line 1189 of file core_cm23.h.
| #define DCB_DHCSR_S_SDE_Pos 20U |
DCB DHCSR: Secure debug enabled Position
Definition at line 1191 of file core_cm23.h.
| #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) |
DCB DHCSR: Secure debug enabled Mask
Definition at line 1192 of file core_cm23.h.
| #define DCB_DHCSR_S_LOCKUP_Pos 19U |
DCB DHCSR: Lockup status Position
Definition at line 1194 of file core_cm23.h.
| #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) |
DCB DHCSR: Lockup status Mask
Definition at line 1195 of file core_cm23.h.
| #define DCB_DHCSR_S_SLEEP_Pos 18U |
DCB DHCSR: Sleeping status Position
Definition at line 1197 of file core_cm23.h.
| #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) |
DCB DHCSR: Sleeping status Mask
Definition at line 1198 of file core_cm23.h.
| #define DCB_DHCSR_S_HALT_Pos 17U |
DCB DHCSR: Halted status Position
Definition at line 1200 of file core_cm23.h.
| #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) |
DCB DHCSR: Halted status Mask
Definition at line 1201 of file core_cm23.h.
| #define DCB_DHCSR_S_REGRDY_Pos 16U |
DCB DHCSR: Register ready status Position
Definition at line 1203 of file core_cm23.h.
| #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) |
DCB DHCSR: Register ready status Mask
Definition at line 1204 of file core_cm23.h.
| #define DCB_DHCSR_C_MASKINTS_Pos 3U |
DCB DHCSR: Mask interrupts control Position
Definition at line 1206 of file core_cm23.h.
| #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) |
DCB DHCSR: Mask interrupts control Mask
Definition at line 1207 of file core_cm23.h.
| #define DCB_DHCSR_C_STEP_Pos 2U |
DCB DHCSR: Step control Position
Definition at line 1209 of file core_cm23.h.
| #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) |
DCB DHCSR: Step control Mask
Definition at line 1210 of file core_cm23.h.
| #define DCB_DHCSR_C_HALT_Pos 1U |
DCB DHCSR: Halt control Position
Definition at line 1212 of file core_cm23.h.
| #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) |
DCB DHCSR: Halt control Mask
Definition at line 1213 of file core_cm23.h.
| #define DCB_DHCSR_C_DEBUGEN_Pos 0U |
DCB DHCSR: Debug enable control Position
Definition at line 1215 of file core_cm23.h.
| #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) |
DCB DHCSR: Debug enable control Mask
Definition at line 1216 of file core_cm23.h.
| #define DCB_DCRSR_REGWnR_Pos 16U |
DCB DCRSR: Register write/not-read Position
Definition at line 1219 of file core_cm23.h.
| #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) |
DCB DCRSR: Register write/not-read Mask
Definition at line 1220 of file core_cm23.h.
| #define DCB_DCRSR_REGSEL_Pos 0U |
DCB DCRSR: Register selector Position
Definition at line 1222 of file core_cm23.h.
| #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) |
DCB DCRSR: Register selector Mask
Definition at line 1223 of file core_cm23.h.
| #define DCB_DCRDR_DBGTMP_Pos 0U |
DCB DCRDR: Data temporary buffer Position
Definition at line 1226 of file core_cm23.h.
| #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) |
DCB DCRDR: Data temporary buffer Mask
Definition at line 1227 of file core_cm23.h.
| #define DCB_DEMCR_TRCENA_Pos 24U |
DCB DEMCR: Trace enable Position
Definition at line 1230 of file core_cm23.h.
| #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) |
DCB DEMCR: Trace enable Mask
Definition at line 1231 of file core_cm23.h.
| #define DCB_DEMCR_VC_HARDERR_Pos 10U |
DCB DEMCR: Vector Catch HardFault errors Position
Definition at line 1233 of file core_cm23.h.
| #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) |
DCB DEMCR: Vector Catch HardFault errors Mask
Definition at line 1234 of file core_cm23.h.
| #define DCB_DEMCR_VC_CORERESET_Pos 0U |
DCB DEMCR: Vector Catch Core reset Position
Definition at line 1236 of file core_cm23.h.
| #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) |
DCB DEMCR: Vector Catch Core reset Mask
Definition at line 1237 of file core_cm23.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position
Definition at line 1240 of file core_cm23.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask
Definition at line 1241 of file core_cm23.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U |
DCB DAUTHCTRL: Secure non-invasive debug enable select Position
Definition at line 1243 of file core_cm23.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) |
DCB DAUTHCTRL: Secure non-invasive debug enable select Mask
Definition at line 1244 of file core_cm23.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U |
DCB DAUTHCTRL: Internal Secure invasive debug enable Position
Definition at line 1246 of file core_cm23.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure invasive debug enable Mask
Definition at line 1247 of file core_cm23.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U |
DCB DAUTHCTRL: Secure invasive debug enable select Position
Definition at line 1249 of file core_cm23.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) |
DCB DAUTHCTRL: Secure invasive debug enable select Mask
Definition at line 1250 of file core_cm23.h.
| #define DCB_DSCSR_CDSKEY_Pos 17U |
DCB DSCSR: CDS write-enable key Position
Definition at line 1253 of file core_cm23.h.
| #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) |
DCB DSCSR: CDS write-enable key Mask
Definition at line 1254 of file core_cm23.h.
| #define DCB_DSCSR_CDS_Pos 16U |
DCB DSCSR: Current domain Secure Position
Definition at line 1256 of file core_cm23.h.
| #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) |
DCB DSCSR: Current domain Secure Mask
Definition at line 1257 of file core_cm23.h.
| #define DCB_DSCSR_SBRSEL_Pos 1U |
DCB DSCSR: Secure banked register select Position
Definition at line 1259 of file core_cm23.h.
| #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) |
DCB DSCSR: Secure banked register select Mask
Definition at line 1260 of file core_cm23.h.
| #define DCB_DSCSR_SBRSELEN_Pos 0U |
DCB DSCSR: Secure banked register select enable Position
Definition at line 1262 of file core_cm23.h.
| #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) |
DCB DSCSR: Secure banked register select enable Mask
Definition at line 1263 of file core_cm23.h.
| #define DIB_DLAR_KEY_Pos 0U |
DIB DLAR: KEY Position
Definition at line 1289 of file core_cm23.h.
| #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) |
DIB DLAR: KEY Mask
Definition at line 1290 of file core_cm23.h.
| #define DIB_DLSR_nTT_Pos 2U |
DIB DLSR: Not thirty-two bit Position
Definition at line 1293 of file core_cm23.h.
| #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) |
DIB DLSR: Not thirty-two bit Mask
Definition at line 1294 of file core_cm23.h.
| #define DIB_DLSR_SLK_Pos 1U |
DIB DLSR: Software Lock status Position
Definition at line 1296 of file core_cm23.h.
| #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) |
DIB DLSR: Software Lock status Mask
Definition at line 1297 of file core_cm23.h.
| #define DIB_DLSR_SLI_Pos 0U |
DIB DLSR: Software Lock implemented Position
Definition at line 1299 of file core_cm23.h.
| #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) |
DIB DLSR: Software Lock implemented Mask
Definition at line 1300 of file core_cm23.h.
| #define DIB_DAUTHSTATUS_SNID_Pos 6U |
DIB DAUTHSTATUS: Secure Non-invasive Debug Position
Definition at line 1303 of file core_cm23.h.
| #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) |
DIB DAUTHSTATUS: Secure Non-invasive Debug Mask
Definition at line 1304 of file core_cm23.h.
| #define DIB_DAUTHSTATUS_SID_Pos 4U |
DIB DAUTHSTATUS: Secure Invasive Debug Position
Definition at line 1306 of file core_cm23.h.
| #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) |
DIB DAUTHSTATUS: Secure Invasive Debug Mask
Definition at line 1307 of file core_cm23.h.
| #define DIB_DAUTHSTATUS_NSNID_Pos 2U |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position
Definition at line 1309 of file core_cm23.h.
| #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask
Definition at line 1310 of file core_cm23.h.
| #define DIB_DAUTHSTATUS_NSID_Pos 0U |
DIB DAUTHSTATUS: Non-secure Invasive Debug Position
Definition at line 1312 of file core_cm23.h.
| #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) |
DIB DAUTHSTATUS: Non-secure Invasive Debug Mask
Definition at line 1313 of file core_cm23.h.
| #define DIB_DDEVARCH_ARCHITECT_Pos 21U |
DIB DDEVARCH: Architect Position
Definition at line 1316 of file core_cm23.h.
| #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) |
DIB DDEVARCH: Architect Mask
Definition at line 1317 of file core_cm23.h.
| #define DIB_DDEVARCH_PRESENT_Pos 20U |
DIB DDEVARCH: DEVARCH Present Position
Definition at line 1319 of file core_cm23.h.
| #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) |
DIB DDEVARCH: DEVARCH Present Mask
Definition at line 1320 of file core_cm23.h.
| #define DIB_DDEVARCH_REVISION_Pos 16U |
DIB DDEVARCH: Revision Position
Definition at line 1322 of file core_cm23.h.
| #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) |
DIB DDEVARCH: Revision Mask
Definition at line 1323 of file core_cm23.h.
| #define DIB_DDEVARCH_ARCHVER_Pos 12U |
DIB DDEVARCH: Architecture Version Position
Definition at line 1325 of file core_cm23.h.
| #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) |
DIB DDEVARCH: Architecture Version Mask
Definition at line 1326 of file core_cm23.h.
| #define DIB_DDEVARCH_ARCHPART_Pos 0U |
DIB DDEVARCH: Architecture Part Position
Definition at line 1328 of file core_cm23.h.
| #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) |
DIB DDEVARCH: Architecture Part Mask
Definition at line 1329 of file core_cm23.h.
| #define DIB_DDEVTYPE_SUB_Pos 4U |
DIB DDEVTYPE: Sub-type Position
Definition at line 1332 of file core_cm23.h.
| #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) |
DIB DDEVTYPE: Sub-type Mask
Definition at line 1333 of file core_cm23.h.
| #define DIB_DDEVTYPE_MAJOR_Pos 0U |
DIB DDEVTYPE: Major type Position
Definition at line 1335 of file core_cm23.h.
| #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) |
DIB DDEVTYPE: Major type Mask
Definition at line 1336 of file core_cm23.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 1355 of file core_cm23.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 1363 of file core_cm23.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 1376 of file core_cm23.h.
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
Definition at line 1377 of file core_cm23.h.
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
Definition at line 1378 of file core_cm23.h.
| #define DCB_BASE (0xE000EDF0UL) |
DCB Base Address
Definition at line 1380 of file core_cm23.h.
| #define DIB_BASE (0xE000EFB0UL) |
DIB Base Address
Definition at line 1381 of file core_cm23.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 1382 of file core_cm23.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 1383 of file core_cm23.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 1384 of file core_cm23.h.
SCB configuration struct
Definition at line 1387 of file core_cm23.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 1388 of file core_cm23.h.
NVIC configuration struct
Definition at line 1389 of file core_cm23.h.
DWT configuration struct
Definition at line 1390 of file core_cm23.h.
TPI configuration struct
Definition at line 1391 of file core_cm23.h.
DCB configuration struct
Definition at line 1393 of file core_cm23.h.
DIB configuration struct
Definition at line 1394 of file core_cm23.h.
| #define MPU_BASE (SCS_BASE + 0x0D90UL) |
Memory Protection Unit
Definition at line 1397 of file core_cm23.h.
Memory Protection Unit
Definition at line 1398 of file core_cm23.h.
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
Definition at line 363 of file core_cm3.h.
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
Definition at line 364 of file core_cm3.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 405 of file core_cm3.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 406 of file core_cm3.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 408 of file core_cm3.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 409 of file core_cm3.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 411 of file core_cm3.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 412 of file core_cm3.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 414 of file core_cm3.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 415 of file core_cm3.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 417 of file core_cm3.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 418 of file core_cm3.h.
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
Definition at line 421 of file core_cm3.h.
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
Definition at line 422 of file core_cm3.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 424 of file core_cm3.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 425 of file core_cm3.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 427 of file core_cm3.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 428 of file core_cm3.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 430 of file core_cm3.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 431 of file core_cm3.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 433 of file core_cm3.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 434 of file core_cm3.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 436 of file core_cm3.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 437 of file core_cm3.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 439 of file core_cm3.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 440 of file core_cm3.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 442 of file core_cm3.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 443 of file core_cm3.h.
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
Definition at line 445 of file core_cm3.h.
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
Definition at line 446 of file core_cm3.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 448 of file core_cm3.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 449 of file core_cm3.h.
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
Definition at line 459 of file core_cm3.h.
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
Definition at line 460 of file core_cm3.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 464 of file core_cm3.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 465 of file core_cm3.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 467 of file core_cm3.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 468 of file core_cm3.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 470 of file core_cm3.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 471 of file core_cm3.h.
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
Definition at line 473 of file core_cm3.h.
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
Definition at line 474 of file core_cm3.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 476 of file core_cm3.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 477 of file core_cm3.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 479 of file core_cm3.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 480 of file core_cm3.h.
| #define SCB_AIRCR_VECTRESET_Pos 0U |
SCB AIRCR: VECTRESET Position
Definition at line 482 of file core_cm3.h.
| #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) |
SCB AIRCR: VECTRESET Mask
Definition at line 483 of file core_cm3.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 486 of file core_cm3.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 487 of file core_cm3.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 489 of file core_cm3.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 490 of file core_cm3.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 492 of file core_cm3.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 493 of file core_cm3.h.
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
Definition at line 496 of file core_cm3.h.
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
Definition at line 497 of file core_cm3.h.
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
Definition at line 499 of file core_cm3.h.
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
Definition at line 500 of file core_cm3.h.
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
Definition at line 502 of file core_cm3.h.
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
Definition at line 503 of file core_cm3.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 505 of file core_cm3.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 506 of file core_cm3.h.
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
Definition at line 508 of file core_cm3.h.
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
Definition at line 509 of file core_cm3.h.
| #define SCB_CCR_NONBASETHRDENA_Pos 0U |
SCB CCR: NONBASETHRDENA Position
Definition at line 511 of file core_cm3.h.
| #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) |
SCB CCR: NONBASETHRDENA Mask
Definition at line 512 of file core_cm3.h.
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
Definition at line 515 of file core_cm3.h.
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
Definition at line 516 of file core_cm3.h.
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
Definition at line 518 of file core_cm3.h.
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
Definition at line 519 of file core_cm3.h.
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
Definition at line 521 of file core_cm3.h.
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
Definition at line 522 of file core_cm3.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 524 of file core_cm3.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 525 of file core_cm3.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
Definition at line 527 of file core_cm3.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
Definition at line 528 of file core_cm3.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
Definition at line 530 of file core_cm3.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
Definition at line 531 of file core_cm3.h.
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
Definition at line 533 of file core_cm3.h.
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
Definition at line 534 of file core_cm3.h.
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
Definition at line 536 of file core_cm3.h.
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
Definition at line 537 of file core_cm3.h.
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
Definition at line 539 of file core_cm3.h.
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
Definition at line 540 of file core_cm3.h.
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
Definition at line 542 of file core_cm3.h.
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
Definition at line 543 of file core_cm3.h.
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
Definition at line 545 of file core_cm3.h.
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
Definition at line 546 of file core_cm3.h.
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
Definition at line 548 of file core_cm3.h.
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
Definition at line 549 of file core_cm3.h.
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
Definition at line 551 of file core_cm3.h.
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
Definition at line 552 of file core_cm3.h.
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
Definition at line 554 of file core_cm3.h.
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
Definition at line 555 of file core_cm3.h.
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
Definition at line 558 of file core_cm3.h.
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
Definition at line 559 of file core_cm3.h.
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
Definition at line 561 of file core_cm3.h.
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
Definition at line 562 of file core_cm3.h.
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
Definition at line 564 of file core_cm3.h.
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
Definition at line 565 of file core_cm3.h.
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
Definition at line 568 of file core_cm3.h.
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
Definition at line 569 of file core_cm3.h.
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
Definition at line 571 of file core_cm3.h.
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
Definition at line 572 of file core_cm3.h.
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
Definition at line 574 of file core_cm3.h.
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
Definition at line 575 of file core_cm3.h.
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
Definition at line 577 of file core_cm3.h.
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
Definition at line 578 of file core_cm3.h.
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
Definition at line 580 of file core_cm3.h.
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
Definition at line 581 of file core_cm3.h.
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
Definition at line 584 of file core_cm3.h.
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
Definition at line 585 of file core_cm3.h.
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
Definition at line 587 of file core_cm3.h.
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
Definition at line 588 of file core_cm3.h.
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
Definition at line 590 of file core_cm3.h.
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
Definition at line 591 of file core_cm3.h.
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
Definition at line 593 of file core_cm3.h.
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
Definition at line 594 of file core_cm3.h.
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
Definition at line 596 of file core_cm3.h.
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
Definition at line 597 of file core_cm3.h.
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
Definition at line 599 of file core_cm3.h.
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
Definition at line 600 of file core_cm3.h.
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
Definition at line 603 of file core_cm3.h.
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
Definition at line 604 of file core_cm3.h.
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
Definition at line 606 of file core_cm3.h.
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
Definition at line 607 of file core_cm3.h.
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
Definition at line 609 of file core_cm3.h.
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
Definition at line 610 of file core_cm3.h.
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
Definition at line 612 of file core_cm3.h.
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
Definition at line 613 of file core_cm3.h.
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
Definition at line 615 of file core_cm3.h.
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
Definition at line 616 of file core_cm3.h.
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
Definition at line 618 of file core_cm3.h.
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
Definition at line 619 of file core_cm3.h.
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
Definition at line 622 of file core_cm3.h.
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
Definition at line 623 of file core_cm3.h.
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
Definition at line 625 of file core_cm3.h.
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
Definition at line 626 of file core_cm3.h.
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
Definition at line 628 of file core_cm3.h.
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
Definition at line 629 of file core_cm3.h.
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
Definition at line 632 of file core_cm3.h.
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
Definition at line 633 of file core_cm3.h.
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
Definition at line 635 of file core_cm3.h.
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
Definition at line 636 of file core_cm3.h.
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
Definition at line 638 of file core_cm3.h.
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
Definition at line 639 of file core_cm3.h.
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
Definition at line 641 of file core_cm3.h.
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
Definition at line 642 of file core_cm3.h.
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
Definition at line 644 of file core_cm3.h.
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
Definition at line 645 of file core_cm3.h.
| #define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
Definition at line 672 of file core_cm3.h.
| #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
Definition at line 673 of file core_cm3.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 715 of file core_cm3.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 716 of file core_cm3.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 718 of file core_cm3.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 719 of file core_cm3.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 721 of file core_cm3.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 722 of file core_cm3.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 724 of file core_cm3.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 725 of file core_cm3.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 728 of file core_cm3.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 729 of file core_cm3.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 732 of file core_cm3.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 733 of file core_cm3.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 736 of file core_cm3.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 737 of file core_cm3.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 739 of file core_cm3.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 740 of file core_cm3.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 742 of file core_cm3.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 743 of file core_cm3.h.
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
Definition at line 792 of file core_cm3.h.
| #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
Definition at line 793 of file core_cm3.h.
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
Definition at line 796 of file core_cm3.h.
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
Definition at line 797 of file core_cm3.h.
| #define ITM_TCR_TraceBusID_Pos 16U |
ITM TCR: ATBID Position
Definition at line 799 of file core_cm3.h.
| #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) |
ITM TCR: ATBID Mask
Definition at line 800 of file core_cm3.h.
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
Definition at line 802 of file core_cm3.h.
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
Definition at line 803 of file core_cm3.h.
| #define ITM_TCR_TSPrescale_Pos 8U |
ITM TCR: TSPrescale Position
Definition at line 805 of file core_cm3.h.
| #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) |
ITM TCR: TSPrescale Mask
Definition at line 806 of file core_cm3.h.
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
Definition at line 808 of file core_cm3.h.
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
Definition at line 809 of file core_cm3.h.
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
Definition at line 811 of file core_cm3.h.
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
Definition at line 812 of file core_cm3.h.
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
Definition at line 814 of file core_cm3.h.
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
Definition at line 815 of file core_cm3.h.
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
Definition at line 817 of file core_cm3.h.
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
Definition at line 818 of file core_cm3.h.
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
Definition at line 820 of file core_cm3.h.
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
Definition at line 821 of file core_cm3.h.
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
Definition at line 824 of file core_cm3.h.
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
Definition at line 825 of file core_cm3.h.
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
Definition at line 827 of file core_cm3.h.
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
Definition at line 828 of file core_cm3.h.
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
Definition at line 830 of file core_cm3.h.
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
Definition at line 831 of file core_cm3.h.
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
Definition at line 874 of file core_cm3.h.
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
Definition at line 875 of file core_cm3.h.
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
Definition at line 877 of file core_cm3.h.
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
Definition at line 878 of file core_cm3.h.
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
Definition at line 880 of file core_cm3.h.
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
Definition at line 881 of file core_cm3.h.
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
Definition at line 883 of file core_cm3.h.
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
Definition at line 884 of file core_cm3.h.
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
Definition at line 886 of file core_cm3.h.
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
Definition at line 887 of file core_cm3.h.
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
Definition at line 889 of file core_cm3.h.
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
Definition at line 890 of file core_cm3.h.
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
Definition at line 892 of file core_cm3.h.
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
Definition at line 893 of file core_cm3.h.
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
Definition at line 895 of file core_cm3.h.
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
Definition at line 896 of file core_cm3.h.
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
Definition at line 898 of file core_cm3.h.
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
Definition at line 899 of file core_cm3.h.
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
Definition at line 901 of file core_cm3.h.
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
Definition at line 902 of file core_cm3.h.
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
Definition at line 904 of file core_cm3.h.
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
Definition at line 905 of file core_cm3.h.
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
Definition at line 907 of file core_cm3.h.
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
Definition at line 908 of file core_cm3.h.
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
Definition at line 910 of file core_cm3.h.
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
Definition at line 911 of file core_cm3.h.
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
Definition at line 913 of file core_cm3.h.
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
Definition at line 914 of file core_cm3.h.
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
Definition at line 916 of file core_cm3.h.
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
Definition at line 917 of file core_cm3.h.
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
Definition at line 919 of file core_cm3.h.
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
Definition at line 920 of file core_cm3.h.
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
Definition at line 922 of file core_cm3.h.
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
Definition at line 923 of file core_cm3.h.
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
Definition at line 925 of file core_cm3.h.
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
Definition at line 926 of file core_cm3.h.
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
Definition at line 929 of file core_cm3.h.
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
Definition at line 930 of file core_cm3.h.
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
Definition at line 933 of file core_cm3.h.
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
Definition at line 934 of file core_cm3.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
Definition at line 937 of file core_cm3.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
Definition at line 938 of file core_cm3.h.
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
Definition at line 941 of file core_cm3.h.
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
Definition at line 942 of file core_cm3.h.
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
Definition at line 945 of file core_cm3.h.
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
Definition at line 946 of file core_cm3.h.
| #define DWT_MASK_MASK_Pos 0U |
DWT MASK: MASK Position
Definition at line 949 of file core_cm3.h.
| #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) |
DWT MASK: MASK Mask
Definition at line 950 of file core_cm3.h.
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
Definition at line 953 of file core_cm3.h.
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
Definition at line 954 of file core_cm3.h.
| #define DWT_FUNCTION_DATAVADDR1_Pos 16U |
DWT FUNCTION: DATAVADDR1 Position
Definition at line 956 of file core_cm3.h.
| #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) |
DWT FUNCTION: DATAVADDR1 Mask
Definition at line 957 of file core_cm3.h.
| #define DWT_FUNCTION_DATAVADDR0_Pos 12U |
DWT FUNCTION: DATAVADDR0 Position
Definition at line 959 of file core_cm3.h.
| #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) |
DWT FUNCTION: DATAVADDR0 Mask
Definition at line 960 of file core_cm3.h.
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
Definition at line 962 of file core_cm3.h.
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
Definition at line 963 of file core_cm3.h.
| #define DWT_FUNCTION_LNK1ENA_Pos 9U |
DWT FUNCTION: LNK1ENA Position
Definition at line 965 of file core_cm3.h.
| #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) |
DWT FUNCTION: LNK1ENA Mask
Definition at line 966 of file core_cm3.h.
| #define DWT_FUNCTION_DATAVMATCH_Pos 8U |
DWT FUNCTION: DATAVMATCH Position
Definition at line 968 of file core_cm3.h.
| #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) |
DWT FUNCTION: DATAVMATCH Mask
Definition at line 969 of file core_cm3.h.
| #define DWT_FUNCTION_CYCMATCH_Pos 7U |
DWT FUNCTION: CYCMATCH Position
Definition at line 971 of file core_cm3.h.
| #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) |
DWT FUNCTION: CYCMATCH Mask
Definition at line 972 of file core_cm3.h.
| #define DWT_FUNCTION_EMITRANGE_Pos 5U |
DWT FUNCTION: EMITRANGE Position
Definition at line 974 of file core_cm3.h.
| #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) |
DWT FUNCTION: EMITRANGE Mask
Definition at line 975 of file core_cm3.h.
| #define DWT_FUNCTION_FUNCTION_Pos 0U |
DWT FUNCTION: FUNCTION Position
Definition at line 977 of file core_cm3.h.
| #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) |
DWT FUNCTION: FUNCTION Mask
Definition at line 978 of file core_cm3.h.
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
Definition at line 1022 of file core_cm3.h.
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
Definition at line 1023 of file core_cm3.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 1026 of file core_cm3.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 1027 of file core_cm3.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 1030 of file core_cm3.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 1031 of file core_cm3.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 1033 of file core_cm3.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 1034 of file core_cm3.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 1036 of file core_cm3.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 1037 of file core_cm3.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 1039 of file core_cm3.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 1040 of file core_cm3.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 1043 of file core_cm3.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 1044 of file core_cm3.h.
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
Definition at line 1046 of file core_cm3.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 1047 of file core_cm3.h.
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
Definition at line 1050 of file core_cm3.h.
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
Definition at line 1051 of file core_cm3.h.
| #define TPI_FIFO0_ITM_ATVALID_Pos 29U |
TPI FIFO0: ITM_ATVALID Position
Definition at line 1054 of file core_cm3.h.
| #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
Definition at line 1055 of file core_cm3.h.
| #define TPI_FIFO0_ITM_bytecount_Pos 27U |
TPI FIFO0: ITM_bytecount Position
Definition at line 1057 of file core_cm3.h.
| #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
Definition at line 1058 of file core_cm3.h.
| #define TPI_FIFO0_ETM_ATVALID_Pos 26U |
TPI FIFO0: ETM_ATVALID Position
Definition at line 1060 of file core_cm3.h.
| #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
Definition at line 1061 of file core_cm3.h.
| #define TPI_FIFO0_ETM_bytecount_Pos 24U |
TPI FIFO0: ETM_bytecount Position
Definition at line 1063 of file core_cm3.h.
| #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
Definition at line 1064 of file core_cm3.h.
| #define TPI_FIFO0_ETM2_Pos 16U |
TPI FIFO0: ETM2 Position
Definition at line 1066 of file core_cm3.h.
| #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
Definition at line 1067 of file core_cm3.h.
| #define TPI_FIFO0_ETM1_Pos 8U |
TPI FIFO0: ETM1 Position
Definition at line 1069 of file core_cm3.h.
| #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
Definition at line 1070 of file core_cm3.h.
| #define TPI_FIFO0_ETM0_Pos 0U |
TPI FIFO0: ETM0 Position
Definition at line 1072 of file core_cm3.h.
| #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
TPI FIFO0: ETM0 Mask
Definition at line 1073 of file core_cm3.h.
| #define TPI_ITATBCTR2_ATREADY2_Pos 0U |
TPI ITATBCTR2: ATREADY2 Position
Definition at line 1076 of file core_cm3.h.
| #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) |
TPI ITATBCTR2: ATREADY2 Mask
Definition at line 1077 of file core_cm3.h.
| #define TPI_ITATBCTR2_ATREADY1_Pos 0U |
TPI ITATBCTR2: ATREADY1 Position
Definition at line 1079 of file core_cm3.h.
| #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) |
TPI ITATBCTR2: ATREADY1 Mask
Definition at line 1080 of file core_cm3.h.
| #define TPI_FIFO1_ITM_ATVALID_Pos 29U |
TPI FIFO1: ITM_ATVALID Position
Definition at line 1083 of file core_cm3.h.
| #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
Definition at line 1084 of file core_cm3.h.
| #define TPI_FIFO1_ITM_bytecount_Pos 27U |
TPI FIFO1: ITM_bytecount Position
Definition at line 1086 of file core_cm3.h.
| #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
Definition at line 1087 of file core_cm3.h.
| #define TPI_FIFO1_ETM_ATVALID_Pos 26U |
TPI FIFO1: ETM_ATVALID Position
Definition at line 1089 of file core_cm3.h.
| #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
Definition at line 1090 of file core_cm3.h.
| #define TPI_FIFO1_ETM_bytecount_Pos 24U |
TPI FIFO1: ETM_bytecount Position
Definition at line 1092 of file core_cm3.h.
| #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
Definition at line 1093 of file core_cm3.h.
| #define TPI_FIFO1_ITM2_Pos 16U |
TPI FIFO1: ITM2 Position
Definition at line 1095 of file core_cm3.h.
| #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
Definition at line 1096 of file core_cm3.h.
| #define TPI_FIFO1_ITM1_Pos 8U |
TPI FIFO1: ITM1 Position
Definition at line 1098 of file core_cm3.h.
| #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
Definition at line 1099 of file core_cm3.h.
| #define TPI_FIFO1_ITM0_Pos 0U |
TPI FIFO1: ITM0 Position
Definition at line 1101 of file core_cm3.h.
| #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
TPI FIFO1: ITM0 Mask
Definition at line 1102 of file core_cm3.h.
| #define TPI_ITATBCTR0_ATREADY2_Pos 0U |
TPI ITATBCTR0: ATREADY2 Position
Definition at line 1105 of file core_cm3.h.
| #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) |
TPI ITATBCTR0: ATREADY2 Mask
Definition at line 1106 of file core_cm3.h.
| #define TPI_ITATBCTR0_ATREADY1_Pos 0U |
TPI ITATBCTR0: ATREADY1 Position
Definition at line 1108 of file core_cm3.h.
| #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) |
TPI ITATBCTR0: ATREADY1 Mask
Definition at line 1109 of file core_cm3.h.
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
Definition at line 1112 of file core_cm3.h.
| #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
Definition at line 1113 of file core_cm3.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 1116 of file core_cm3.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1117 of file core_cm3.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 1119 of file core_cm3.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1120 of file core_cm3.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 1122 of file core_cm3.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1123 of file core_cm3.h.
| #define TPI_DEVID_MinBufSz_Pos 6U |
TPI DEVID: MinBufSz Position
Definition at line 1125 of file core_cm3.h.
| #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
Definition at line 1126 of file core_cm3.h.
| #define TPI_DEVID_AsynClkIn_Pos 5U |
TPI DEVID: AsynClkIn Position
Definition at line 1128 of file core_cm3.h.
| #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
Definition at line 1129 of file core_cm3.h.
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
Definition at line 1131 of file core_cm3.h.
| #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
Definition at line 1132 of file core_cm3.h.
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
Definition at line 1135 of file core_cm3.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 1136 of file core_cm3.h.
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
Definition at line 1138 of file core_cm3.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1139 of file core_cm3.h.
| #define MPU_TYPE_IREGION_Pos 16U |
MPU TYPE: IREGION Position
Definition at line 1173 of file core_cm3.h.
| #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) |
MPU TYPE: IREGION Mask
Definition at line 1174 of file core_cm3.h.
| #define MPU_TYPE_DREGION_Pos 8U |
MPU TYPE: DREGION Position
Definition at line 1176 of file core_cm3.h.
| #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) |
MPU TYPE: DREGION Mask
Definition at line 1177 of file core_cm3.h.
| #define MPU_TYPE_SEPARATE_Pos 0U |
MPU TYPE: SEPARATE Position
Definition at line 1179 of file core_cm3.h.
| #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) |
MPU TYPE: SEPARATE Mask
Definition at line 1180 of file core_cm3.h.
| #define MPU_CTRL_PRIVDEFENA_Pos 2U |
MPU CTRL: PRIVDEFENA Position
Definition at line 1183 of file core_cm3.h.
| #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) |
MPU CTRL: PRIVDEFENA Mask
Definition at line 1184 of file core_cm3.h.
| #define MPU_CTRL_HFNMIENA_Pos 1U |
MPU CTRL: HFNMIENA Position
Definition at line 1186 of file core_cm3.h.
| #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) |
MPU CTRL: HFNMIENA Mask
Definition at line 1187 of file core_cm3.h.
| #define MPU_CTRL_ENABLE_Pos 0U |
MPU CTRL: ENABLE Position
Definition at line 1189 of file core_cm3.h.
| #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) |
MPU CTRL: ENABLE Mask
Definition at line 1190 of file core_cm3.h.
| #define MPU_RNR_REGION_Pos 0U |
MPU RNR: REGION Position
Definition at line 1193 of file core_cm3.h.
| #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) |
MPU RNR: REGION Mask
Definition at line 1194 of file core_cm3.h.
| #define MPU_RBAR_ADDR_Pos 5U |
MPU RBAR: ADDR Position
Definition at line 1197 of file core_cm3.h.
| #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) |
MPU RBAR: ADDR Mask
Definition at line 1198 of file core_cm3.h.
| #define MPU_RBAR_VALID_Pos 4U |
MPU RBAR: VALID Position
Definition at line 1200 of file core_cm3.h.
| #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) |
MPU RBAR: VALID Mask
Definition at line 1201 of file core_cm3.h.
| #define MPU_RBAR_REGION_Pos 0U |
MPU RBAR: REGION Position
Definition at line 1203 of file core_cm3.h.
| #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) |
MPU RBAR: REGION Mask
Definition at line 1204 of file core_cm3.h.
| #define MPU_RASR_ATTRS_Pos 16U |
MPU RASR: MPU Region Attribute field Position
Definition at line 1207 of file core_cm3.h.
| #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) |
MPU RASR: MPU Region Attribute field Mask
Definition at line 1208 of file core_cm3.h.
| #define MPU_RASR_XN_Pos 28U |
MPU RASR: ATTRS.XN Position
Definition at line 1210 of file core_cm3.h.
| #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) |
MPU RASR: ATTRS.XN Mask
Definition at line 1211 of file core_cm3.h.
| #define MPU_RASR_AP_Pos 24U |
MPU RASR: ATTRS.AP Position
Definition at line 1213 of file core_cm3.h.
| #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) |
MPU RASR: ATTRS.AP Mask
Definition at line 1214 of file core_cm3.h.
| #define MPU_RASR_TEX_Pos 19U |
MPU RASR: ATTRS.TEX Position
Definition at line 1216 of file core_cm3.h.
| #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) |
MPU RASR: ATTRS.TEX Mask
Definition at line 1217 of file core_cm3.h.
| #define MPU_RASR_S_Pos 18U |
MPU RASR: ATTRS.S Position
Definition at line 1219 of file core_cm3.h.
| #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) |
MPU RASR: ATTRS.S Mask
Definition at line 1220 of file core_cm3.h.
| #define MPU_RASR_C_Pos 17U |
MPU RASR: ATTRS.C Position
Definition at line 1222 of file core_cm3.h.
| #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) |
MPU RASR: ATTRS.C Mask
Definition at line 1223 of file core_cm3.h.
| #define MPU_RASR_B_Pos 16U |
MPU RASR: ATTRS.B Position
Definition at line 1225 of file core_cm3.h.
| #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) |
MPU RASR: ATTRS.B Mask
Definition at line 1226 of file core_cm3.h.
| #define MPU_RASR_SRD_Pos 8U |
MPU RASR: Sub-Region Disable Position
Definition at line 1228 of file core_cm3.h.
| #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) |
MPU RASR: Sub-Region Disable Mask
Definition at line 1229 of file core_cm3.h.
| #define MPU_RASR_SIZE_Pos 1U |
MPU RASR: Region Size Field Position
Definition at line 1231 of file core_cm3.h.
| #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) |
MPU RASR: Region Size Field Mask
Definition at line 1232 of file core_cm3.h.
| #define MPU_RASR_ENABLE_Pos 0U |
MPU RASR: Region enable bit Position
Definition at line 1234 of file core_cm3.h.
| #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) |
MPU RASR: Region enable bit Disable Mask
Definition at line 1235 of file core_cm3.h.
| #define CoreDebug_DHCSR_DBGKEY_Pos 16U |
CoreDebug DHCSR: DBGKEY Position
Definition at line 1260 of file core_cm3.h.
| #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
CoreDebug DHCSR: DBGKEY Mask
Definition at line 1261 of file core_cm3.h.
| #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
CoreDebug DHCSR: S_RESET_ST Position
Definition at line 1263 of file core_cm3.h.
| #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
CoreDebug DHCSR: S_RESET_ST Mask
Definition at line 1264 of file core_cm3.h.
| #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
CoreDebug DHCSR: S_RETIRE_ST Position
Definition at line 1266 of file core_cm3.h.
| #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
CoreDebug DHCSR: S_RETIRE_ST Mask
Definition at line 1267 of file core_cm3.h.
| #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
CoreDebug DHCSR: S_LOCKUP Position
Definition at line 1269 of file core_cm3.h.
| #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
CoreDebug DHCSR: S_LOCKUP Mask
Definition at line 1270 of file core_cm3.h.
| #define CoreDebug_DHCSR_S_SLEEP_Pos 18U |
CoreDebug DHCSR: S_SLEEP Position
Definition at line 1272 of file core_cm3.h.
| #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
CoreDebug DHCSR: S_SLEEP Mask
Definition at line 1273 of file core_cm3.h.
| #define CoreDebug_DHCSR_S_HALT_Pos 17U |
CoreDebug DHCSR: S_HALT Position
Definition at line 1275 of file core_cm3.h.
| #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
CoreDebug DHCSR: S_HALT Mask
Definition at line 1276 of file core_cm3.h.
| #define CoreDebug_DHCSR_S_REGRDY_Pos 16U |
CoreDebug DHCSR: S_REGRDY Position
Definition at line 1278 of file core_cm3.h.
| #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
CoreDebug DHCSR: S_REGRDY Mask
Definition at line 1279 of file core_cm3.h.
| #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U |
CoreDebug DHCSR: C_SNAPSTALL Position
Definition at line 1281 of file core_cm3.h.
| #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) |
CoreDebug DHCSR: C_SNAPSTALL Mask
Definition at line 1282 of file core_cm3.h.
| #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
CoreDebug DHCSR: C_MASKINTS Position
Definition at line 1284 of file core_cm3.h.
| #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
CoreDebug DHCSR: C_MASKINTS Mask
Definition at line 1285 of file core_cm3.h.
| #define CoreDebug_DHCSR_C_STEP_Pos 2U |
CoreDebug DHCSR: C_STEP Position
Definition at line 1287 of file core_cm3.h.
| #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
CoreDebug DHCSR: C_STEP Mask
Definition at line 1288 of file core_cm3.h.
| #define CoreDebug_DHCSR_C_HALT_Pos 1U |
CoreDebug DHCSR: C_HALT Position
Definition at line 1290 of file core_cm3.h.
| #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
CoreDebug DHCSR: C_HALT Mask
Definition at line 1291 of file core_cm3.h.
| #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
CoreDebug DHCSR: C_DEBUGEN Position
Definition at line 1293 of file core_cm3.h.
| #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
CoreDebug DHCSR: C_DEBUGEN Mask
Definition at line 1294 of file core_cm3.h.
| #define CoreDebug_DCRSR_REGWnR_Pos 16U |
CoreDebug DCRSR: REGWnR Position
Definition at line 1297 of file core_cm3.h.
| #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
CoreDebug DCRSR: REGWnR Mask
Definition at line 1298 of file core_cm3.h.
| #define CoreDebug_DCRSR_REGSEL_Pos 0U |
CoreDebug DCRSR: REGSEL Position
Definition at line 1300 of file core_cm3.h.
| #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
CoreDebug DCRSR: REGSEL Mask
Definition at line 1301 of file core_cm3.h.
| #define CoreDebug_DEMCR_TRCENA_Pos 24U |
CoreDebug DEMCR: TRCENA Position
Definition at line 1304 of file core_cm3.h.
| #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) |
CoreDebug DEMCR: TRCENA Mask
Definition at line 1305 of file core_cm3.h.
| #define CoreDebug_DEMCR_MON_REQ_Pos 19U |
CoreDebug DEMCR: MON_REQ Position
Definition at line 1307 of file core_cm3.h.
| #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) |
CoreDebug DEMCR: MON_REQ Mask
Definition at line 1308 of file core_cm3.h.
| #define CoreDebug_DEMCR_MON_STEP_Pos 18U |
CoreDebug DEMCR: MON_STEP Position
Definition at line 1310 of file core_cm3.h.
| #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) |
CoreDebug DEMCR: MON_STEP Mask
Definition at line 1311 of file core_cm3.h.
| #define CoreDebug_DEMCR_MON_PEND_Pos 17U |
CoreDebug DEMCR: MON_PEND Position
Definition at line 1313 of file core_cm3.h.
| #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) |
CoreDebug DEMCR: MON_PEND Mask
Definition at line 1314 of file core_cm3.h.
| #define CoreDebug_DEMCR_MON_EN_Pos 16U |
CoreDebug DEMCR: MON_EN Position
Definition at line 1316 of file core_cm3.h.
| #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) |
CoreDebug DEMCR: MON_EN Mask
Definition at line 1317 of file core_cm3.h.
| #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
CoreDebug DEMCR: VC_HARDERR Position
Definition at line 1319 of file core_cm3.h.
| #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
CoreDebug DEMCR: VC_HARDERR Mask
Definition at line 1320 of file core_cm3.h.
| #define CoreDebug_DEMCR_VC_INTERR_Pos 9U |
CoreDebug DEMCR: VC_INTERR Position
Definition at line 1322 of file core_cm3.h.
| #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) |
CoreDebug DEMCR: VC_INTERR Mask
Definition at line 1323 of file core_cm3.h.
| #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U |
CoreDebug DEMCR: VC_BUSERR Position
Definition at line 1325 of file core_cm3.h.
| #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) |
CoreDebug DEMCR: VC_BUSERR Mask
Definition at line 1326 of file core_cm3.h.
| #define CoreDebug_DEMCR_VC_STATERR_Pos 7U |
CoreDebug DEMCR: VC_STATERR Position
Definition at line 1328 of file core_cm3.h.
| #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) |
CoreDebug DEMCR: VC_STATERR Mask
Definition at line 1329 of file core_cm3.h.
| #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U |
CoreDebug DEMCR: VC_CHKERR Position
Definition at line 1331 of file core_cm3.h.
| #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) |
CoreDebug DEMCR: VC_CHKERR Mask
Definition at line 1332 of file core_cm3.h.
| #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U |
CoreDebug DEMCR: VC_NOCPERR Position
Definition at line 1334 of file core_cm3.h.
| #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) |
CoreDebug DEMCR: VC_NOCPERR Mask
Definition at line 1335 of file core_cm3.h.
| #define CoreDebug_DEMCR_VC_MMERR_Pos 4U |
CoreDebug DEMCR: VC_MMERR Position
Definition at line 1337 of file core_cm3.h.
| #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) |
CoreDebug DEMCR: VC_MMERR Mask
Definition at line 1338 of file core_cm3.h.
| #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
CoreDebug DEMCR: VC_CORERESET Position
Definition at line 1340 of file core_cm3.h.
| #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
CoreDebug DEMCR: VC_CORERESET Mask
Definition at line 1341 of file core_cm3.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 1359 of file core_cm3.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 1367 of file core_cm3.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 1380 of file core_cm3.h.
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
Definition at line 1381 of file core_cm3.h.
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
Definition at line 1382 of file core_cm3.h.
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
Definition at line 1383 of file core_cm3.h.
| #define CoreDebug_BASE (0xE000EDF0UL) |
Core Debug Base Address
Definition at line 1384 of file core_cm3.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 1385 of file core_cm3.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 1386 of file core_cm3.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 1387 of file core_cm3.h.
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
Definition at line 1389 of file core_cm3.h.
SCB configuration struct
Definition at line 1390 of file core_cm3.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 1391 of file core_cm3.h.
NVIC configuration struct
Definition at line 1392 of file core_cm3.h.
ITM configuration struct
Definition at line 1393 of file core_cm3.h.
DWT configuration struct
Definition at line 1394 of file core_cm3.h.
TPI configuration struct
Definition at line 1395 of file core_cm3.h.
| #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) |
Core Debug configuration struct
Definition at line 1396 of file core_cm3.h.
| #define MPU_BASE (SCS_BASE + 0x0D90UL) |
Memory Protection Unit
Definition at line 1399 of file core_cm3.h.
Memory Protection Unit
Definition at line 1400 of file core_cm3.h.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 1867 of file core_cm3.h.
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
Definition at line 488 of file core_cm33.h.
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
Definition at line 489 of file core_cm33.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 555 of file core_cm33.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 556 of file core_cm33.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 558 of file core_cm33.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 559 of file core_cm33.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 561 of file core_cm33.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 562 of file core_cm33.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 564 of file core_cm33.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 565 of file core_cm33.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 567 of file core_cm33.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 568 of file core_cm33.h.
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
Definition at line 571 of file core_cm33.h.
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
Definition at line 572 of file core_cm33.h.
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
Definition at line 574 of file core_cm33.h.
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
Definition at line 575 of file core_cm33.h.
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
Definition at line 577 of file core_cm33.h.
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
Definition at line 578 of file core_cm33.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 580 of file core_cm33.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 581 of file core_cm33.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 583 of file core_cm33.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 584 of file core_cm33.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 586 of file core_cm33.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 587 of file core_cm33.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 589 of file core_cm33.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 590 of file core_cm33.h.
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
Definition at line 592 of file core_cm33.h.
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
Definition at line 593 of file core_cm33.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 595 of file core_cm33.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 596 of file core_cm33.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 598 of file core_cm33.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 599 of file core_cm33.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 601 of file core_cm33.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 602 of file core_cm33.h.
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
Definition at line 604 of file core_cm33.h.
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
Definition at line 605 of file core_cm33.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 607 of file core_cm33.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 608 of file core_cm33.h.
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
Definition at line 611 of file core_cm33.h.
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
Definition at line 612 of file core_cm33.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 615 of file core_cm33.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 616 of file core_cm33.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 618 of file core_cm33.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 619 of file core_cm33.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 621 of file core_cm33.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 622 of file core_cm33.h.
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
Definition at line 624 of file core_cm33.h.
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
Definition at line 625 of file core_cm33.h.
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
Definition at line 627 of file core_cm33.h.
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
Definition at line 628 of file core_cm33.h.
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
Definition at line 630 of file core_cm33.h.
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
Definition at line 631 of file core_cm33.h.
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
Definition at line 633 of file core_cm33.h.
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
Definition at line 634 of file core_cm33.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 636 of file core_cm33.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 637 of file core_cm33.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 639 of file core_cm33.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 640 of file core_cm33.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 643 of file core_cm33.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 644 of file core_cm33.h.
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
Definition at line 646 of file core_cm33.h.
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
Definition at line 647 of file core_cm33.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 649 of file core_cm33.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 650 of file core_cm33.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 652 of file core_cm33.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 653 of file core_cm33.h.
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
SCB CCR: Branch prediction enable bit Position
Definition at line 656 of file core_cm33.h.
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
SCB CCR: Branch prediction enable bit Mask
Definition at line 657 of file core_cm33.h.
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
SCB CCR: Instruction cache enable bit Position
Definition at line 659 of file core_cm33.h.
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
SCB CCR: Instruction cache enable bit Mask
Definition at line 660 of file core_cm33.h.
| #define SCB_CCR_DC_Pos 16U |
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
Definition at line 665 of file core_cm33.h.
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
Definition at line 666 of file core_cm33.h.
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
Definition at line 668 of file core_cm33.h.
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
Definition at line 669 of file core_cm33.h.
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
Definition at line 671 of file core_cm33.h.
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
Definition at line 672 of file core_cm33.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 674 of file core_cm33.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 675 of file core_cm33.h.
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
Definition at line 677 of file core_cm33.h.
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
Definition at line 678 of file core_cm33.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
Definition at line 681 of file core_cm33.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
Definition at line 682 of file core_cm33.h.
| #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
SCB SHCSR: SECUREFAULTPENDED Position
Definition at line 684 of file core_cm33.h.
| #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
SCB SHCSR: SECUREFAULTPENDED Mask
Definition at line 685 of file core_cm33.h.
| #define SCB_SHCSR_SECUREFAULTENA_Pos 19U |
SCB SHCSR: SECUREFAULTENA Position
Definition at line 687 of file core_cm33.h.
| #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
SCB SHCSR: SECUREFAULTENA Mask
Definition at line 688 of file core_cm33.h.
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
Definition at line 690 of file core_cm33.h.
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
Definition at line 691 of file core_cm33.h.
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
Definition at line 693 of file core_cm33.h.
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
Definition at line 694 of file core_cm33.h.
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
Definition at line 696 of file core_cm33.h.
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
Definition at line 697 of file core_cm33.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 699 of file core_cm33.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 700 of file core_cm33.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
Definition at line 702 of file core_cm33.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
Definition at line 703 of file core_cm33.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
Definition at line 705 of file core_cm33.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
Definition at line 706 of file core_cm33.h.
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
Definition at line 708 of file core_cm33.h.
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
Definition at line 709 of file core_cm33.h.
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
Definition at line 711 of file core_cm33.h.
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
Definition at line 712 of file core_cm33.h.
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
Definition at line 714 of file core_cm33.h.
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
Definition at line 715 of file core_cm33.h.
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
Definition at line 717 of file core_cm33.h.
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
Definition at line 718 of file core_cm33.h.
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
Definition at line 720 of file core_cm33.h.
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
Definition at line 721 of file core_cm33.h.
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
Definition at line 723 of file core_cm33.h.
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
Definition at line 724 of file core_cm33.h.
| #define SCB_SHCSR_SECUREFAULTACT_Pos 4U |
SCB SHCSR: SECUREFAULTACT Position
Definition at line 726 of file core_cm33.h.
| #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
SCB SHCSR: SECUREFAULTACT Mask
Definition at line 727 of file core_cm33.h.
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
Definition at line 729 of file core_cm33.h.
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
Definition at line 730 of file core_cm33.h.
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
Definition at line 732 of file core_cm33.h.
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
Definition at line 733 of file core_cm33.h.
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
Definition at line 735 of file core_cm33.h.
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
Definition at line 736 of file core_cm33.h.
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
Definition at line 738 of file core_cm33.h.
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
Definition at line 739 of file core_cm33.h.
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
Definition at line 742 of file core_cm33.h.
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
Definition at line 743 of file core_cm33.h.
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
Definition at line 745 of file core_cm33.h.
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
Definition at line 746 of file core_cm33.h.
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
Definition at line 748 of file core_cm33.h.
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
Definition at line 749 of file core_cm33.h.
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
Definition at line 752 of file core_cm33.h.
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
Definition at line 753 of file core_cm33.h.
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
Definition at line 755 of file core_cm33.h.
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
Definition at line 756 of file core_cm33.h.
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
Definition at line 758 of file core_cm33.h.
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
Definition at line 759 of file core_cm33.h.
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
Definition at line 761 of file core_cm33.h.
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
Definition at line 762 of file core_cm33.h.
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
Definition at line 764 of file core_cm33.h.
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
Definition at line 765 of file core_cm33.h.
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
Definition at line 767 of file core_cm33.h.
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
Definition at line 768 of file core_cm33.h.
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
Definition at line 771 of file core_cm33.h.
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
Definition at line 772 of file core_cm33.h.
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
Definition at line 774 of file core_cm33.h.
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
Definition at line 775 of file core_cm33.h.
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
Definition at line 777 of file core_cm33.h.
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
Definition at line 778 of file core_cm33.h.
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
Definition at line 780 of file core_cm33.h.
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
Definition at line 781 of file core_cm33.h.
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
Definition at line 783 of file core_cm33.h.
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
Definition at line 784 of file core_cm33.h.
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
Definition at line 786 of file core_cm33.h.
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
Definition at line 787 of file core_cm33.h.
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
Definition at line 789 of file core_cm33.h.
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
Definition at line 790 of file core_cm33.h.
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
Definition at line 793 of file core_cm33.h.
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
Definition at line 794 of file core_cm33.h.
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
Definition at line 796 of file core_cm33.h.
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
Definition at line 797 of file core_cm33.h.
| #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
SCB CFSR (UFSR): STKOF Position
Definition at line 799 of file core_cm33.h.
| #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
SCB CFSR (UFSR): STKOF Mask
Definition at line 800 of file core_cm33.h.
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
Definition at line 802 of file core_cm33.h.
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
Definition at line 803 of file core_cm33.h.
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
Definition at line 805 of file core_cm33.h.
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
Definition at line 806 of file core_cm33.h.
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
Definition at line 808 of file core_cm33.h.
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
Definition at line 809 of file core_cm33.h.
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
Definition at line 811 of file core_cm33.h.
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
Definition at line 812 of file core_cm33.h.
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
Definition at line 815 of file core_cm33.h.
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
Definition at line 816 of file core_cm33.h.
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
Definition at line 818 of file core_cm33.h.
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
Definition at line 819 of file core_cm33.h.
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
Definition at line 821 of file core_cm33.h.
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
Definition at line 822 of file core_cm33.h.
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
Definition at line 825 of file core_cm33.h.
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
Definition at line 826 of file core_cm33.h.
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
Definition at line 828 of file core_cm33.h.
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
Definition at line 829 of file core_cm33.h.
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
Definition at line 831 of file core_cm33.h.
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
Definition at line 832 of file core_cm33.h.
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
Definition at line 834 of file core_cm33.h.
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
Definition at line 835 of file core_cm33.h.
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
Definition at line 837 of file core_cm33.h.
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
Definition at line 838 of file core_cm33.h.
| #define SCB_NSACR_CP11_Pos 11U |
SCB NSACR: CP11 Position
Definition at line 841 of file core_cm33.h.
| #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
SCB NSACR: CP11 Mask
Definition at line 842 of file core_cm33.h.
| #define SCB_NSACR_CP10_Pos 10U |
SCB NSACR: CP10 Position
Definition at line 844 of file core_cm33.h.
| #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
SCB NSACR: CP10 Mask
Definition at line 845 of file core_cm33.h.
| #define SCB_NSACR_CPn_Pos 0U |
SCB NSACR: CPn Position
Definition at line 847 of file core_cm33.h.
| #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) |
SCB NSACR: CPn Mask
Definition at line 848 of file core_cm33.h.
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
Definition at line 851 of file core_cm33.h.
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
Definition at line 852 of file core_cm33.h.
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
Definition at line 854 of file core_cm33.h.
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
Definition at line 855 of file core_cm33.h.
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
Definition at line 858 of file core_cm33.h.
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
Definition at line 859 of file core_cm33.h.
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
Definition at line 861 of file core_cm33.h.
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
Definition at line 862 of file core_cm33.h.
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
Definition at line 864 of file core_cm33.h.
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
Definition at line 865 of file core_cm33.h.
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
Definition at line 867 of file core_cm33.h.
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
Definition at line 868 of file core_cm33.h.
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
Definition at line 870 of file core_cm33.h.
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
Definition at line 871 of file core_cm33.h.
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
Definition at line 874 of file core_cm33.h.
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
Definition at line 875 of file core_cm33.h.
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
Definition at line 877 of file core_cm33.h.
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
Definition at line 878 of file core_cm33.h.
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
Definition at line 880 of file core_cm33.h.
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
Definition at line 881 of file core_cm33.h.
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
Definition at line 883 of file core_cm33.h.
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
Definition at line 884 of file core_cm33.h.
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
Definition at line 886 of file core_cm33.h.
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
Definition at line 887 of file core_cm33.h.
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
Definition at line 889 of file core_cm33.h.
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
Definition at line 890 of file core_cm33.h.
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
Definition at line 892 of file core_cm33.h.
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
Definition at line 893 of file core_cm33.h.
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
Definition at line 896 of file core_cm33.h.
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
Definition at line 897 of file core_cm33.h.
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
Definition at line 899 of file core_cm33.h.
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
Definition at line 900 of file core_cm33.h.
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
Definition at line 903 of file core_cm33.h.
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
Definition at line 904 of file core_cm33.h.
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
Definition at line 907 of file core_cm33.h.
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
Definition at line 908 of file core_cm33.h.
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
Definition at line 910 of file core_cm33.h.
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
Definition at line 911 of file core_cm33.h.
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
Definition at line 914 of file core_cm33.h.
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
Definition at line 915 of file core_cm33.h.
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
Definition at line 917 of file core_cm33.h.
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
Definition at line 918 of file core_cm33.h.
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
Definition at line 921 of file core_cm33.h.
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
Definition at line 922 of file core_cm33.h.
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
Definition at line 924 of file core_cm33.h.
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
Definition at line 925 of file core_cm33.h.
| #define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
Definition at line 949 of file core_cm33.h.
| #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
Definition at line 950 of file core_cm33.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 974 of file core_cm33.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 975 of file core_cm33.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 977 of file core_cm33.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 978 of file core_cm33.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 980 of file core_cm33.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 981 of file core_cm33.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 983 of file core_cm33.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 984 of file core_cm33.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 987 of file core_cm33.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 988 of file core_cm33.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 991 of file core_cm33.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 992 of file core_cm33.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 995 of file core_cm33.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 996 of file core_cm33.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 998 of file core_cm33.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 999 of file core_cm33.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 1001 of file core_cm33.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 1002 of file core_cm33.h.
| #define ITM_STIM_DISABLED_Pos 1U |
ITM STIM: DISABLED Position
Definition at line 1053 of file core_cm33.h.
| #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) |
ITM STIM: DISABLED Mask
Definition at line 1054 of file core_cm33.h.
| #define ITM_STIM_FIFOREADY_Pos 0U |
ITM STIM: FIFOREADY Position
Definition at line 1056 of file core_cm33.h.
| #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) |
ITM STIM: FIFOREADY Mask
Definition at line 1057 of file core_cm33.h.
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
Definition at line 1060 of file core_cm33.h.
| #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
Definition at line 1061 of file core_cm33.h.
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
Definition at line 1064 of file core_cm33.h.
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
Definition at line 1065 of file core_cm33.h.
| #define ITM_TCR_TRACEBUSID_Pos 16U |
ITM TCR: ATBID Position
Definition at line 1067 of file core_cm33.h.
| #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) |
ITM TCR: ATBID Mask
Definition at line 1068 of file core_cm33.h.
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
Definition at line 1070 of file core_cm33.h.
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
Definition at line 1071 of file core_cm33.h.
| #define ITM_TCR_TSPRESCALE_Pos 8U |
ITM TCR: TSPRESCALE Position
Definition at line 1073 of file core_cm33.h.
| #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) |
ITM TCR: TSPRESCALE Mask
Definition at line 1074 of file core_cm33.h.
| #define ITM_TCR_STALLENA_Pos 5U |
ITM TCR: STALLENA Position
Definition at line 1076 of file core_cm33.h.
| #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) |
ITM TCR: STALLENA Mask
Definition at line 1077 of file core_cm33.h.
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
Definition at line 1079 of file core_cm33.h.
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
Definition at line 1080 of file core_cm33.h.
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
Definition at line 1082 of file core_cm33.h.
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
Definition at line 1083 of file core_cm33.h.
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
Definition at line 1085 of file core_cm33.h.
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
Definition at line 1086 of file core_cm33.h.
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
Definition at line 1088 of file core_cm33.h.
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
Definition at line 1089 of file core_cm33.h.
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
Definition at line 1091 of file core_cm33.h.
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
Definition at line 1092 of file core_cm33.h.
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
Definition at line 1095 of file core_cm33.h.
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
Definition at line 1096 of file core_cm33.h.
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
Definition at line 1098 of file core_cm33.h.
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
Definition at line 1099 of file core_cm33.h.
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
Definition at line 1101 of file core_cm33.h.
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
Definition at line 1102 of file core_cm33.h.
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
Definition at line 1197 of file core_cm33.h.
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
Definition at line 1198 of file core_cm33.h.
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
Definition at line 1200 of file core_cm33.h.
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
Definition at line 1201 of file core_cm33.h.
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
Definition at line 1203 of file core_cm33.h.
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
Definition at line 1204 of file core_cm33.h.
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
Definition at line 1206 of file core_cm33.h.
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
Definition at line 1207 of file core_cm33.h.
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
Definition at line 1209 of file core_cm33.h.
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
Definition at line 1210 of file core_cm33.h.
| #define DWT_CTRL_CYCDISS_Pos 23U |
DWT CTRL: CYCDISS Position
Definition at line 1212 of file core_cm33.h.
| #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) |
DWT CTRL: CYCDISS Mask
Definition at line 1213 of file core_cm33.h.
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
Definition at line 1215 of file core_cm33.h.
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
Definition at line 1216 of file core_cm33.h.
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
Definition at line 1218 of file core_cm33.h.
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
Definition at line 1219 of file core_cm33.h.
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
Definition at line 1221 of file core_cm33.h.
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
Definition at line 1222 of file core_cm33.h.
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
Definition at line 1224 of file core_cm33.h.
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
Definition at line 1225 of file core_cm33.h.
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
Definition at line 1227 of file core_cm33.h.
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
Definition at line 1228 of file core_cm33.h.
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
Definition at line 1230 of file core_cm33.h.
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
Definition at line 1231 of file core_cm33.h.
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
Definition at line 1233 of file core_cm33.h.
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
Definition at line 1234 of file core_cm33.h.
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
Definition at line 1236 of file core_cm33.h.
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
Definition at line 1237 of file core_cm33.h.
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
Definition at line 1239 of file core_cm33.h.
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
Definition at line 1240 of file core_cm33.h.
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
Definition at line 1242 of file core_cm33.h.
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
Definition at line 1243 of file core_cm33.h.
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
Definition at line 1245 of file core_cm33.h.
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
Definition at line 1246 of file core_cm33.h.
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
Definition at line 1248 of file core_cm33.h.
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
Definition at line 1249 of file core_cm33.h.
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
Definition at line 1251 of file core_cm33.h.
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
Definition at line 1252 of file core_cm33.h.
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
Definition at line 1255 of file core_cm33.h.
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
Definition at line 1256 of file core_cm33.h.
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
Definition at line 1259 of file core_cm33.h.
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
Definition at line 1260 of file core_cm33.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
Definition at line 1263 of file core_cm33.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
Definition at line 1264 of file core_cm33.h.
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
Definition at line 1267 of file core_cm33.h.
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
Definition at line 1268 of file core_cm33.h.
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
Definition at line 1271 of file core_cm33.h.
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
Definition at line 1272 of file core_cm33.h.
| #define DWT_FUNCTION_ID_Pos 27U |
DWT FUNCTION: ID Position
Definition at line 1275 of file core_cm33.h.
| #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) |
DWT FUNCTION: ID Mask
Definition at line 1276 of file core_cm33.h.
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
Definition at line 1278 of file core_cm33.h.
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
Definition at line 1279 of file core_cm33.h.
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
Definition at line 1281 of file core_cm33.h.
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
Definition at line 1282 of file core_cm33.h.
| #define DWT_FUNCTION_ACTION_Pos 4U |
DWT FUNCTION: ACTION Position
Definition at line 1284 of file core_cm33.h.
| #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) |
DWT FUNCTION: ACTION Mask
Definition at line 1285 of file core_cm33.h.
| #define DWT_FUNCTION_MATCH_Pos 0U |
DWT FUNCTION: MATCH Position
Definition at line 1287 of file core_cm33.h.
| #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) |
DWT FUNCTION: MATCH Mask
Definition at line 1288 of file core_cm33.h.
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
Definition at line 1332 of file core_cm33.h.
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
Definition at line 1333 of file core_cm33.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 1336 of file core_cm33.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 1337 of file core_cm33.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 1340 of file core_cm33.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 1341 of file core_cm33.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 1343 of file core_cm33.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 1344 of file core_cm33.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 1346 of file core_cm33.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 1347 of file core_cm33.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 1349 of file core_cm33.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 1350 of file core_cm33.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 1353 of file core_cm33.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 1354 of file core_cm33.h.
| #define TPI_FFCR_FOnMan_Pos 6U |
TPI FFCR: FOnMan Position
Definition at line 1356 of file core_cm33.h.
| #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) |
TPI FFCR: FOnMan Mask
Definition at line 1357 of file core_cm33.h.
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
Definition at line 1359 of file core_cm33.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 1360 of file core_cm33.h.
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
Definition at line 1363 of file core_cm33.h.
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
Definition at line 1364 of file core_cm33.h.
| #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U |
TPI ITFTTD0: ATB Interface 2 ATVALIDPosition
Definition at line 1367 of file core_cm33.h.
| #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) |
TPI ITFTTD0: ATB Interface 2 ATVALID Mask
Definition at line 1368 of file core_cm33.h.
| #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U |
TPI ITFTTD0: ATB Interface 2 byte count Position
Definition at line 1370 of file core_cm33.h.
| #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) |
TPI ITFTTD0: ATB Interface 2 byte count Mask
Definition at line 1371 of file core_cm33.h.
| #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U |
TPI ITFTTD0: ATB Interface 1 ATVALID Position
Definition at line 1373 of file core_cm33.h.
| #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) |
TPI ITFTTD0: ATB Interface 1 ATVALID Mask
Definition at line 1374 of file core_cm33.h.
| #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U |
TPI ITFTTD0: ATB Interface 1 byte count Position
Definition at line 1376 of file core_cm33.h.
| #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) |
TPI ITFTTD0: ATB Interface 1 byte countt Mask
Definition at line 1377 of file core_cm33.h.
| #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U |
TPI ITFTTD0: ATB Interface 1 data2 Position
Definition at line 1379 of file core_cm33.h.
| #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) |
TPI ITFTTD0: ATB Interface 1 data2 Mask
Definition at line 1380 of file core_cm33.h.
| #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U |
TPI ITFTTD0: ATB Interface 1 data1 Position
Definition at line 1382 of file core_cm33.h.
| #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) |
TPI ITFTTD0: ATB Interface 1 data1 Mask
Definition at line 1383 of file core_cm33.h.
| #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U |
TPI ITFTTD0: ATB Interface 1 data0 Position
Definition at line 1385 of file core_cm33.h.
| #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) |
TPI ITFTTD0: ATB Interface 1 data0 Mask
Definition at line 1386 of file core_cm33.h.
| #define TPI_ITATBCTR2_AFVALID2S_Pos 1U |
TPI ITATBCTR2: AFVALID2S Position
Definition at line 1389 of file core_cm33.h.
| #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) |
TPI ITATBCTR2: AFVALID2SS Mask
Definition at line 1390 of file core_cm33.h.
| #define TPI_ITATBCTR2_AFVALID1S_Pos 1U |
TPI ITATBCTR2: AFVALID1S Position
Definition at line 1392 of file core_cm33.h.
| #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) |
TPI ITATBCTR2: AFVALID1SS Mask
Definition at line 1393 of file core_cm33.h.
| #define TPI_ITATBCTR2_ATREADY2S_Pos 0U |
TPI ITATBCTR2: ATREADY2S Position
Definition at line 1395 of file core_cm33.h.
| #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) |
TPI ITATBCTR2: ATREADY2S Mask
Definition at line 1396 of file core_cm33.h.
| #define TPI_ITATBCTR2_ATREADY1S_Pos 0U |
TPI ITATBCTR2: ATREADY1S Position
Definition at line 1398 of file core_cm33.h.
| #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) |
TPI ITATBCTR2: ATREADY1S Mask
Definition at line 1399 of file core_cm33.h.
| #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U |
TPI ITFTTD1: ATB Interface 2 ATVALID Position
Definition at line 1402 of file core_cm33.h.
| #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) |
TPI ITFTTD1: ATB Interface 2 ATVALID Mask
Definition at line 1403 of file core_cm33.h.
| #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U |
TPI ITFTTD1: ATB Interface 2 byte count Position
Definition at line 1405 of file core_cm33.h.
| #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) |
TPI ITFTTD1: ATB Interface 2 byte count Mask
Definition at line 1406 of file core_cm33.h.
| #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U |
TPI ITFTTD1: ATB Interface 1 ATVALID Position
Definition at line 1408 of file core_cm33.h.
| #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) |
TPI ITFTTD1: ATB Interface 1 ATVALID Mask
Definition at line 1409 of file core_cm33.h.
| #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U |
TPI ITFTTD1: ATB Interface 1 byte count Position
Definition at line 1411 of file core_cm33.h.
| #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) |
TPI ITFTTD1: ATB Interface 1 byte countt Mask
Definition at line 1412 of file core_cm33.h.
| #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U |
TPI ITFTTD1: ATB Interface 2 data2 Position
Definition at line 1414 of file core_cm33.h.
| #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) |
TPI ITFTTD1: ATB Interface 2 data2 Mask
Definition at line 1415 of file core_cm33.h.
| #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U |
TPI ITFTTD1: ATB Interface 2 data1 Position
Definition at line 1417 of file core_cm33.h.
| #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) |
TPI ITFTTD1: ATB Interface 2 data1 Mask
Definition at line 1418 of file core_cm33.h.
| #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U |
TPI ITFTTD1: ATB Interface 2 data0 Position
Definition at line 1420 of file core_cm33.h.
| #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) |
TPI ITFTTD1: ATB Interface 2 data0 Mask
Definition at line 1421 of file core_cm33.h.
| #define TPI_ITATBCTR0_AFVALID2S_Pos 1U |
TPI ITATBCTR0: AFVALID2S Position
Definition at line 1424 of file core_cm33.h.
| #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) |
TPI ITATBCTR0: AFVALID2SS Mask
Definition at line 1425 of file core_cm33.h.
| #define TPI_ITATBCTR0_AFVALID1S_Pos 1U |
TPI ITATBCTR0: AFVALID1S Position
Definition at line 1427 of file core_cm33.h.
| #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) |
TPI ITATBCTR0: AFVALID1SS Mask
Definition at line 1428 of file core_cm33.h.
| #define TPI_ITATBCTR0_ATREADY2S_Pos 0U |
TPI ITATBCTR0: ATREADY2S Position
Definition at line 1430 of file core_cm33.h.
| #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) |
TPI ITATBCTR0: ATREADY2S Mask
Definition at line 1431 of file core_cm33.h.
| #define TPI_ITATBCTR0_ATREADY1S_Pos 0U |
TPI ITATBCTR0: ATREADY1S Position
Definition at line 1433 of file core_cm33.h.
| #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) |
TPI ITATBCTR0: ATREADY1S Mask
Definition at line 1434 of file core_cm33.h.
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
Definition at line 1437 of file core_cm33.h.
| #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
Definition at line 1438 of file core_cm33.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 1441 of file core_cm33.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1442 of file core_cm33.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 1444 of file core_cm33.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1445 of file core_cm33.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 1447 of file core_cm33.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1448 of file core_cm33.h.
| #define TPI_DEVID_FIFOSZ_Pos 6U |
TPI DEVID: FIFOSZ Position
TPI DEVID: FIFO depth Position
Definition at line 1450 of file core_cm33.h.
| #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) |
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
Definition at line 1453 of file core_cm33.h.
| #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
Definition at line 1454 of file core_cm33.h.
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
Definition at line 1457 of file core_cm33.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 1458 of file core_cm33.h.
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
Definition at line 1460 of file core_cm33.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1461 of file core_cm33.h.
| #define MPU_TYPE_IREGION_Pos 16U |
MPU TYPE: IREGION Position
Definition at line 1503 of file core_cm33.h.
| #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) |
MPU TYPE: IREGION Mask
Definition at line 1504 of file core_cm33.h.
| #define MPU_TYPE_DREGION_Pos 8U |
MPU TYPE: DREGION Position
Definition at line 1506 of file core_cm33.h.
| #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) |
MPU TYPE: DREGION Mask
Definition at line 1507 of file core_cm33.h.
| #define MPU_TYPE_SEPARATE_Pos 0U |
MPU TYPE: SEPARATE Position
Definition at line 1509 of file core_cm33.h.
| #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) |
MPU TYPE: SEPARATE Mask
Definition at line 1510 of file core_cm33.h.
| #define MPU_CTRL_PRIVDEFENA_Pos 2U |
MPU CTRL: PRIVDEFENA Position
Definition at line 1513 of file core_cm33.h.
| #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) |
MPU CTRL: PRIVDEFENA Mask
Definition at line 1514 of file core_cm33.h.
| #define MPU_CTRL_HFNMIENA_Pos 1U |
MPU CTRL: HFNMIENA Position
Definition at line 1516 of file core_cm33.h.
| #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) |
MPU CTRL: HFNMIENA Mask
Definition at line 1517 of file core_cm33.h.
| #define MPU_CTRL_ENABLE_Pos 0U |
MPU CTRL: ENABLE Position
Definition at line 1519 of file core_cm33.h.
| #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) |
MPU CTRL: ENABLE Mask
Definition at line 1520 of file core_cm33.h.
| #define MPU_RNR_REGION_Pos 0U |
MPU RNR: REGION Position
Definition at line 1523 of file core_cm33.h.
| #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) |
MPU RNR: REGION Mask
Definition at line 1524 of file core_cm33.h.
| #define MPU_RBAR_BASE_Pos 5U |
MPU RBAR: BASE Position
Definition at line 1527 of file core_cm33.h.
| #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) |
MPU RBAR: BASE Mask
Definition at line 1528 of file core_cm33.h.
| #define MPU_RBAR_SH_Pos 3U |
MPU RBAR: SH Position
Definition at line 1530 of file core_cm33.h.
| #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) |
MPU RBAR: SH Mask
Definition at line 1531 of file core_cm33.h.
| #define MPU_RBAR_AP_Pos 1U |
MPU RBAR: AP Position
Definition at line 1533 of file core_cm33.h.
| #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) |
MPU RBAR: AP Mask
Definition at line 1534 of file core_cm33.h.
| #define MPU_RBAR_XN_Pos 0U |
MPU RBAR: XN Position
Definition at line 1536 of file core_cm33.h.
| #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) |
MPU RBAR: XN Mask
Definition at line 1537 of file core_cm33.h.
| #define MPU_RLAR_LIMIT_Pos 5U |
MPU RLAR: LIMIT Position
Definition at line 1540 of file core_cm33.h.
| #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) |
MPU RLAR: LIMIT Mask
Definition at line 1541 of file core_cm33.h.
| #define MPU_RLAR_AttrIndx_Pos 1U |
MPU RLAR: AttrIndx Position
Definition at line 1543 of file core_cm33.h.
| #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) |
MPU RLAR: AttrIndx Mask
Definition at line 1544 of file core_cm33.h.
| #define MPU_RLAR_EN_Pos 0U |
MPU RLAR: Region enable bit Position
Definition at line 1546 of file core_cm33.h.
| #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) |
MPU RLAR: Region enable bit Disable Mask
Definition at line 1547 of file core_cm33.h.
| #define MPU_MAIR0_Attr3_Pos 24U |
MPU MAIR0: Attr3 Position
Definition at line 1550 of file core_cm33.h.
| #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) |
MPU MAIR0: Attr3 Mask
Definition at line 1551 of file core_cm33.h.
| #define MPU_MAIR0_Attr2_Pos 16U |
MPU MAIR0: Attr2 Position
Definition at line 1553 of file core_cm33.h.
| #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) |
MPU MAIR0: Attr2 Mask
Definition at line 1554 of file core_cm33.h.
| #define MPU_MAIR0_Attr1_Pos 8U |
MPU MAIR0: Attr1 Position
Definition at line 1556 of file core_cm33.h.
| #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) |
MPU MAIR0: Attr1 Mask
Definition at line 1557 of file core_cm33.h.
| #define MPU_MAIR0_Attr0_Pos 0U |
MPU MAIR0: Attr0 Position
Definition at line 1559 of file core_cm33.h.
| #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) |
MPU MAIR0: Attr0 Mask
Definition at line 1560 of file core_cm33.h.
| #define MPU_MAIR1_Attr7_Pos 24U |
MPU MAIR1: Attr7 Position
Definition at line 1563 of file core_cm33.h.
| #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) |
MPU MAIR1: Attr7 Mask
Definition at line 1564 of file core_cm33.h.
| #define MPU_MAIR1_Attr6_Pos 16U |
MPU MAIR1: Attr6 Position
Definition at line 1566 of file core_cm33.h.
| #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) |
MPU MAIR1: Attr6 Mask
Definition at line 1567 of file core_cm33.h.
| #define MPU_MAIR1_Attr5_Pos 8U |
MPU MAIR1: Attr5 Position
Definition at line 1569 of file core_cm33.h.
| #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) |
MPU MAIR1: Attr5 Mask
Definition at line 1570 of file core_cm33.h.
| #define MPU_MAIR1_Attr4_Pos 0U |
MPU MAIR1: Attr4 Position
Definition at line 1572 of file core_cm33.h.
| #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) |
MPU MAIR1: Attr4 Mask
Definition at line 1573 of file core_cm33.h.
| #define FPU_FPCCR_ASPEN_Pos 31U |
FPCCR: ASPEN bit Position
Definition at line 1688 of file core_cm33.h.
| #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) |
FPCCR: ASPEN bit Mask
Definition at line 1689 of file core_cm33.h.
| #define FPU_FPCCR_LSPEN_Pos 30U |
FPCCR: LSPEN Position
Definition at line 1691 of file core_cm33.h.
| #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) |
FPCCR: LSPEN bit Mask
Definition at line 1692 of file core_cm33.h.
| #define FPU_FPCCR_LSPENS_Pos 29U |
FPCCR: LSPENS Position
Definition at line 1694 of file core_cm33.h.
| #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) |
FPCCR: LSPENS bit Mask
Definition at line 1695 of file core_cm33.h.
| #define FPU_FPCCR_CLRONRET_Pos 28U |
FPCCR: CLRONRET Position
Definition at line 1697 of file core_cm33.h.
| #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) |
FPCCR: CLRONRET bit Mask
Definition at line 1698 of file core_cm33.h.
| #define FPU_FPCCR_CLRONRETS_Pos 27U |
FPCCR: CLRONRETS Position
Definition at line 1700 of file core_cm33.h.
| #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) |
FPCCR: CLRONRETS bit Mask
Definition at line 1701 of file core_cm33.h.
| #define FPU_FPCCR_TS_Pos 26U |
FPCCR: TS Position
Definition at line 1703 of file core_cm33.h.
| #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) |
FPCCR: TS bit Mask
Definition at line 1704 of file core_cm33.h.
| #define FPU_FPCCR_UFRDY_Pos 10U |
FPCCR: UFRDY Position
Definition at line 1706 of file core_cm33.h.
| #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) |
FPCCR: UFRDY bit Mask
Definition at line 1707 of file core_cm33.h.
| #define FPU_FPCCR_SPLIMVIOL_Pos 9U |
FPCCR: SPLIMVIOL Position
Definition at line 1709 of file core_cm33.h.
| #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) |
FPCCR: SPLIMVIOL bit Mask
Definition at line 1710 of file core_cm33.h.
| #define FPU_FPCCR_MONRDY_Pos 8U |
FPCCR: MONRDY Position
Definition at line 1712 of file core_cm33.h.
| #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) |
FPCCR: MONRDY bit Mask
Definition at line 1713 of file core_cm33.h.
| #define FPU_FPCCR_SFRDY_Pos 7U |
FPCCR: SFRDY Position
Definition at line 1715 of file core_cm33.h.
| #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) |
FPCCR: SFRDY bit Mask
Definition at line 1716 of file core_cm33.h.
| #define FPU_FPCCR_BFRDY_Pos 6U |
FPCCR: BFRDY Position
Definition at line 1718 of file core_cm33.h.
| #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) |
FPCCR: BFRDY bit Mask
Definition at line 1719 of file core_cm33.h.
| #define FPU_FPCCR_MMRDY_Pos 5U |
FPCCR: MMRDY Position
Definition at line 1721 of file core_cm33.h.
| #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) |
FPCCR: MMRDY bit Mask
Definition at line 1722 of file core_cm33.h.
| #define FPU_FPCCR_HFRDY_Pos 4U |
FPCCR: HFRDY Position
Definition at line 1724 of file core_cm33.h.
| #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) |
FPCCR: HFRDY bit Mask
Definition at line 1725 of file core_cm33.h.
| #define FPU_FPCCR_THREAD_Pos 3U |
FPCCR: processor mode bit Position
Definition at line 1727 of file core_cm33.h.
| #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) |
FPCCR: processor mode active bit Mask
Definition at line 1728 of file core_cm33.h.
| #define FPU_FPCCR_S_Pos 2U |
FPCCR: Security status of the FP context bit Position
Definition at line 1730 of file core_cm33.h.
| #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) |
FPCCR: Security status of the FP context bit Mask
Definition at line 1731 of file core_cm33.h.
| #define FPU_FPCCR_USER_Pos 1U |
FPCCR: privilege level bit Position
Definition at line 1733 of file core_cm33.h.
| #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) |
FPCCR: privilege level bit Mask
Definition at line 1734 of file core_cm33.h.
| #define FPU_FPCCR_LSPACT_Pos 0U |
FPCCR: Lazy state preservation active bit Position
Definition at line 1736 of file core_cm33.h.
| #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) |
FPCCR: Lazy state preservation active bit Mask
Definition at line 1737 of file core_cm33.h.
| #define FPU_FPCAR_ADDRESS_Pos 3U |
FPCAR: ADDRESS bit Position
Definition at line 1740 of file core_cm33.h.
| #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) |
FPCAR: ADDRESS bit Mask
Definition at line 1741 of file core_cm33.h.
| #define FPU_FPDSCR_AHP_Pos 26U |
FPDSCR: AHP bit Position
Definition at line 1744 of file core_cm33.h.
| #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) |
FPDSCR: AHP bit Mask
Definition at line 1745 of file core_cm33.h.
| #define FPU_FPDSCR_DN_Pos 25U |
FPDSCR: DN bit Position
Definition at line 1747 of file core_cm33.h.
| #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) |
FPDSCR: DN bit Mask
Definition at line 1748 of file core_cm33.h.
| #define FPU_FPDSCR_FZ_Pos 24U |
FPDSCR: FZ bit Position
Definition at line 1750 of file core_cm33.h.
| #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) |
FPDSCR: FZ bit Mask
Definition at line 1751 of file core_cm33.h.
| #define FPU_FPDSCR_RMode_Pos 22U |
FPDSCR: RMode bit Position
Definition at line 1753 of file core_cm33.h.
| #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) |
FPDSCR: RMode bit Mask
Definition at line 1754 of file core_cm33.h.
| #define FPU_MVFR0_FP_rounding_modes_Pos 28U |
MVFR0: FP rounding modes bits Position
Definition at line 1757 of file core_cm33.h.
| #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) |
MVFR0: FP rounding modes bits Mask
Definition at line 1758 of file core_cm33.h.
| #define FPU_MVFR0_Short_vectors_Pos 24U |
MVFR0: Short vectors bits Position
Definition at line 1760 of file core_cm33.h.
| #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) |
MVFR0: Short vectors bits Mask
Definition at line 1761 of file core_cm33.h.
| #define FPU_MVFR0_Square_root_Pos 20U |
MVFR0: Square root bits Position
Definition at line 1763 of file core_cm33.h.
| #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) |
MVFR0: Square root bits Mask
Definition at line 1764 of file core_cm33.h.
| #define FPU_MVFR0_Divide_Pos 16U |
MVFR0: Divide bits Position
Definition at line 1766 of file core_cm33.h.
| #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) |
MVFR0: Divide bits Mask
Definition at line 1767 of file core_cm33.h.
| #define FPU_MVFR0_FP_excep_trapping_Pos 12U |
MVFR0: FP exception trapping bits Position
Definition at line 1769 of file core_cm33.h.
| #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) |
MVFR0: FP exception trapping bits Mask
Definition at line 1770 of file core_cm33.h.
| #define FPU_MVFR0_Double_precision_Pos 8U |
MVFR0: Double-precision bits Position
Definition at line 1772 of file core_cm33.h.
| #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) |
MVFR0: Double-precision bits Mask
Definition at line 1773 of file core_cm33.h.
| #define FPU_MVFR0_Single_precision_Pos 4U |
MVFR0: Single-precision bits Position
Definition at line 1775 of file core_cm33.h.
| #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) |
MVFR0: Single-precision bits Mask
Definition at line 1776 of file core_cm33.h.
| #define FPU_MVFR0_A_SIMD_registers_Pos 0U |
MVFR0: A_SIMD registers bits Position
Definition at line 1778 of file core_cm33.h.
| #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) |
MVFR0: A_SIMD registers bits Mask
Definition at line 1779 of file core_cm33.h.
| #define FPU_MVFR1_FP_fused_MAC_Pos 28U |
MVFR1: FP fused MAC bits Position
Definition at line 1782 of file core_cm33.h.
| #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) |
MVFR1: FP fused MAC bits Mask
Definition at line 1783 of file core_cm33.h.
| #define FPU_MVFR1_FP_HPFP_Pos 24U |
MVFR1: FP HPFP bits Position
Definition at line 1785 of file core_cm33.h.
| #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) |
MVFR1: FP HPFP bits Mask
Definition at line 1786 of file core_cm33.h.
| #define FPU_MVFR1_D_NaN_mode_Pos 4U |
MVFR1: D_NaN mode bits Position
Definition at line 1788 of file core_cm33.h.
| #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) |
MVFR1: D_NaN mode bits Mask
Definition at line 1789 of file core_cm33.h.
| #define FPU_MVFR1_FtZ_mode_Pos 0U |
MVFR1: FtZ mode bits Position
Definition at line 1791 of file core_cm33.h.
| #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) |
MVFR1: FtZ mode bits Mask
Definition at line 1792 of file core_cm33.h.
| #define FPU_MVFR2_FPMisc_Pos 4U |
MVFR2: FPMisc bits Position
Definition at line 1795 of file core_cm33.h.
| #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) |
MVFR2: FPMisc bits Mask
Definition at line 1796 of file core_cm33.h.
| #define DCB_DHCSR_DBGKEY_Pos 16U |
DCB DHCSR: Debug key Position
Definition at line 1957 of file core_cm33.h.
| #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) |
DCB DHCSR: Debug key Mask
Definition at line 1958 of file core_cm33.h.
| #define DCB_DHCSR_S_RESTART_ST_Pos 26U |
DCB DHCSR: Restart sticky status Position
Definition at line 1960 of file core_cm33.h.
| #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) |
DCB DHCSR: Restart sticky status Mask
Definition at line 1961 of file core_cm33.h.
| #define DCB_DHCSR_S_RESET_ST_Pos 25U |
DCB DHCSR: Reset sticky status Position
Definition at line 1963 of file core_cm33.h.
| #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) |
DCB DHCSR: Reset sticky status Mask
Definition at line 1964 of file core_cm33.h.
| #define DCB_DHCSR_S_RETIRE_ST_Pos 24U |
DCB DHCSR: Retire sticky status Position
Definition at line 1966 of file core_cm33.h.
| #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) |
DCB DHCSR: Retire sticky status Mask
Definition at line 1967 of file core_cm33.h.
| #define DCB_DHCSR_S_SDE_Pos 20U |
DCB DHCSR: Secure debug enabled Position
Definition at line 1969 of file core_cm33.h.
| #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) |
DCB DHCSR: Secure debug enabled Mask
Definition at line 1970 of file core_cm33.h.
| #define DCB_DHCSR_S_LOCKUP_Pos 19U |
DCB DHCSR: Lockup status Position
Definition at line 1972 of file core_cm33.h.
| #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) |
DCB DHCSR: Lockup status Mask
Definition at line 1973 of file core_cm33.h.
| #define DCB_DHCSR_S_SLEEP_Pos 18U |
DCB DHCSR: Sleeping status Position
Definition at line 1975 of file core_cm33.h.
| #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) |
DCB DHCSR: Sleeping status Mask
Definition at line 1976 of file core_cm33.h.
| #define DCB_DHCSR_S_HALT_Pos 17U |
DCB DHCSR: Halted status Position
Definition at line 1978 of file core_cm33.h.
| #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) |
DCB DHCSR: Halted status Mask
Definition at line 1979 of file core_cm33.h.
| #define DCB_DHCSR_S_REGRDY_Pos 16U |
DCB DHCSR: Register ready status Position
Definition at line 1981 of file core_cm33.h.
| #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) |
DCB DHCSR: Register ready status Mask
Definition at line 1982 of file core_cm33.h.
| #define DCB_DHCSR_C_SNAPSTALL_Pos 5U |
DCB DHCSR: Snap stall control Position
Definition at line 1984 of file core_cm33.h.
| #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) |
DCB DHCSR: Snap stall control Mask
Definition at line 1985 of file core_cm33.h.
| #define DCB_DHCSR_C_MASKINTS_Pos 3U |
DCB DHCSR: Mask interrupts control Position
Definition at line 1987 of file core_cm33.h.
| #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) |
DCB DHCSR: Mask interrupts control Mask
Definition at line 1988 of file core_cm33.h.
| #define DCB_DHCSR_C_STEP_Pos 2U |
DCB DHCSR: Step control Position
Definition at line 1990 of file core_cm33.h.
| #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) |
DCB DHCSR: Step control Mask
Definition at line 1991 of file core_cm33.h.
| #define DCB_DHCSR_C_HALT_Pos 1U |
DCB DHCSR: Halt control Position
Definition at line 1993 of file core_cm33.h.
| #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) |
DCB DHCSR: Halt control Mask
Definition at line 1994 of file core_cm33.h.
| #define DCB_DHCSR_C_DEBUGEN_Pos 0U |
DCB DHCSR: Debug enable control Position
Definition at line 1996 of file core_cm33.h.
| #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) |
DCB DHCSR: Debug enable control Mask
Definition at line 1997 of file core_cm33.h.
| #define DCB_DCRSR_REGWnR_Pos 16U |
DCB DCRSR: Register write/not-read Position
Definition at line 2000 of file core_cm33.h.
| #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) |
DCB DCRSR: Register write/not-read Mask
Definition at line 2001 of file core_cm33.h.
| #define DCB_DCRSR_REGSEL_Pos 0U |
DCB DCRSR: Register selector Position
Definition at line 2003 of file core_cm33.h.
| #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) |
DCB DCRSR: Register selector Mask
Definition at line 2004 of file core_cm33.h.
| #define DCB_DCRDR_DBGTMP_Pos 0U |
DCB DCRDR: Data temporary buffer Position
Definition at line 2007 of file core_cm33.h.
| #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) |
DCB DCRDR: Data temporary buffer Mask
Definition at line 2008 of file core_cm33.h.
| #define DCB_DEMCR_TRCENA_Pos 24U |
DCB DEMCR: Trace enable Position
Definition at line 2011 of file core_cm33.h.
| #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) |
DCB DEMCR: Trace enable Mask
Definition at line 2012 of file core_cm33.h.
| #define DCB_DEMCR_MONPRKEY_Pos 23U |
DCB DEMCR: Monitor pend req key Position
Definition at line 2014 of file core_cm33.h.
| #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) |
DCB DEMCR: Monitor pend req key Mask
Definition at line 2015 of file core_cm33.h.
| #define DCB_DEMCR_UMON_EN_Pos 21U |
DCB DEMCR: Unprivileged monitor enable Position
Definition at line 2017 of file core_cm33.h.
| #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) |
DCB DEMCR: Unprivileged monitor enable Mask
Definition at line 2018 of file core_cm33.h.
| #define DCB_DEMCR_SDME_Pos 20U |
DCB DEMCR: Secure DebugMonitor enable Position
Definition at line 2020 of file core_cm33.h.
| #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) |
DCB DEMCR: Secure DebugMonitor enable Mask
Definition at line 2021 of file core_cm33.h.
| #define DCB_DEMCR_MON_REQ_Pos 19U |
DCB DEMCR: Monitor request Position
Definition at line 2023 of file core_cm33.h.
| #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) |
DCB DEMCR: Monitor request Mask
Definition at line 2024 of file core_cm33.h.
| #define DCB_DEMCR_MON_STEP_Pos 18U |
DCB DEMCR: Monitor step Position
Definition at line 2026 of file core_cm33.h.
| #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) |
DCB DEMCR: Monitor step Mask
Definition at line 2027 of file core_cm33.h.
| #define DCB_DEMCR_MON_PEND_Pos 17U |
DCB DEMCR: Monitor pend Position
Definition at line 2029 of file core_cm33.h.
| #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) |
DCB DEMCR: Monitor pend Mask
Definition at line 2030 of file core_cm33.h.
| #define DCB_DEMCR_MON_EN_Pos 16U |
DCB DEMCR: Monitor enable Position
Definition at line 2032 of file core_cm33.h.
| #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) |
DCB DEMCR: Monitor enable Mask
Definition at line 2033 of file core_cm33.h.
| #define DCB_DEMCR_VC_SFERR_Pos 11U |
DCB DEMCR: Vector Catch SecureFault Position
Definition at line 2035 of file core_cm33.h.
| #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) |
DCB DEMCR: Vector Catch SecureFault Mask
Definition at line 2036 of file core_cm33.h.
| #define DCB_DEMCR_VC_HARDERR_Pos 10U |
DCB DEMCR: Vector Catch HardFault errors Position
Definition at line 2038 of file core_cm33.h.
| #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) |
DCB DEMCR: Vector Catch HardFault errors Mask
Definition at line 2039 of file core_cm33.h.
| #define DCB_DEMCR_VC_INTERR_Pos 9U |
DCB DEMCR: Vector Catch interrupt errors Position
Definition at line 2041 of file core_cm33.h.
| #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) |
DCB DEMCR: Vector Catch interrupt errors Mask
Definition at line 2042 of file core_cm33.h.
| #define DCB_DEMCR_VC_BUSERR_Pos 8U |
DCB DEMCR: Vector Catch BusFault errors Position
Definition at line 2044 of file core_cm33.h.
| #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) |
DCB DEMCR: Vector Catch BusFault errors Mask
Definition at line 2045 of file core_cm33.h.
| #define DCB_DEMCR_VC_STATERR_Pos 7U |
DCB DEMCR: Vector Catch state errors Position
Definition at line 2047 of file core_cm33.h.
| #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) |
DCB DEMCR: Vector Catch state errors Mask
Definition at line 2048 of file core_cm33.h.
| #define DCB_DEMCR_VC_CHKERR_Pos 6U |
DCB DEMCR: Vector Catch check errors Position
Definition at line 2050 of file core_cm33.h.
| #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) |
DCB DEMCR: Vector Catch check errors Mask
Definition at line 2051 of file core_cm33.h.
| #define DCB_DEMCR_VC_NOCPERR_Pos 5U |
DCB DEMCR: Vector Catch NOCP errors Position
Definition at line 2053 of file core_cm33.h.
| #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) |
DCB DEMCR: Vector Catch NOCP errors Mask
Definition at line 2054 of file core_cm33.h.
| #define DCB_DEMCR_VC_MMERR_Pos 4U |
DCB DEMCR: Vector Catch MemManage errors Position
Definition at line 2056 of file core_cm33.h.
| #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) |
DCB DEMCR: Vector Catch MemManage errors Mask
Definition at line 2057 of file core_cm33.h.
| #define DCB_DEMCR_VC_CORERESET_Pos 0U |
DCB DEMCR: Vector Catch Core reset Position
Definition at line 2059 of file core_cm33.h.
| #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) |
DCB DEMCR: Vector Catch Core reset Mask
Definition at line 2060 of file core_cm33.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position
Definition at line 2063 of file core_cm33.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask
Definition at line 2064 of file core_cm33.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U |
DCB DAUTHCTRL: Secure non-invasive debug enable select Position
Definition at line 2066 of file core_cm33.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) |
DCB DAUTHCTRL: Secure non-invasive debug enable select Mask
Definition at line 2067 of file core_cm33.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U |
DCB DAUTHCTRL: Internal Secure invasive debug enable Position
Definition at line 2069 of file core_cm33.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure invasive debug enable Mask
Definition at line 2070 of file core_cm33.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U |
DCB DAUTHCTRL: Secure invasive debug enable select Position
Definition at line 2072 of file core_cm33.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) |
DCB DAUTHCTRL: Secure invasive debug enable select Mask
Definition at line 2073 of file core_cm33.h.
| #define DCB_DSCSR_CDSKEY_Pos 17U |
DCB DSCSR: CDS write-enable key Position
Definition at line 2076 of file core_cm33.h.
| #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) |
DCB DSCSR: CDS write-enable key Mask
Definition at line 2077 of file core_cm33.h.
| #define DCB_DSCSR_CDS_Pos 16U |
DCB DSCSR: Current domain Secure Position
Definition at line 2079 of file core_cm33.h.
| #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) |
DCB DSCSR: Current domain Secure Mask
Definition at line 2080 of file core_cm33.h.
| #define DCB_DSCSR_SBRSEL_Pos 1U |
DCB DSCSR: Secure banked register select Position
Definition at line 2082 of file core_cm33.h.
| #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) |
DCB DSCSR: Secure banked register select Mask
Definition at line 2083 of file core_cm33.h.
| #define DCB_DSCSR_SBRSELEN_Pos 0U |
DCB DSCSR: Secure banked register select enable Position
Definition at line 2085 of file core_cm33.h.
| #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) |
DCB DSCSR: Secure banked register select enable Mask
Definition at line 2086 of file core_cm33.h.
| #define DIB_DLAR_KEY_Pos 0U |
DIB DLAR: KEY Position
Definition at line 2112 of file core_cm33.h.
| #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) |
DIB DLAR: KEY Mask
Definition at line 2113 of file core_cm33.h.
| #define DIB_DLSR_nTT_Pos 2U |
DIB DLSR: Not thirty-two bit Position
Definition at line 2116 of file core_cm33.h.
| #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) |
DIB DLSR: Not thirty-two bit Mask
Definition at line 2117 of file core_cm33.h.
| #define DIB_DLSR_SLK_Pos 1U |
DIB DLSR: Software Lock status Position
Definition at line 2119 of file core_cm33.h.
| #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) |
DIB DLSR: Software Lock status Mask
Definition at line 2120 of file core_cm33.h.
| #define DIB_DLSR_SLI_Pos 0U |
DIB DLSR: Software Lock implemented Position
Definition at line 2122 of file core_cm33.h.
| #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) |
DIB DLSR: Software Lock implemented Mask
Definition at line 2123 of file core_cm33.h.
| #define DIB_DAUTHSTATUS_SNID_Pos 6U |
DIB DAUTHSTATUS: Secure Non-invasive Debug Position
Definition at line 2126 of file core_cm33.h.
| #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) |
DIB DAUTHSTATUS: Secure Non-invasive Debug Mask
Definition at line 2127 of file core_cm33.h.
| #define DIB_DAUTHSTATUS_SID_Pos 4U |
DIB DAUTHSTATUS: Secure Invasive Debug Position
Definition at line 2129 of file core_cm33.h.
| #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) |
DIB DAUTHSTATUS: Secure Invasive Debug Mask
Definition at line 2130 of file core_cm33.h.
| #define DIB_DAUTHSTATUS_NSNID_Pos 2U |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position
Definition at line 2132 of file core_cm33.h.
| #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask
Definition at line 2133 of file core_cm33.h.
| #define DIB_DAUTHSTATUS_NSID_Pos 0U |
DIB DAUTHSTATUS: Non-secure Invasive Debug Position
Definition at line 2135 of file core_cm33.h.
| #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) |
DIB DAUTHSTATUS: Non-secure Invasive Debug Mask
Definition at line 2136 of file core_cm33.h.
| #define DIB_DDEVARCH_ARCHITECT_Pos 21U |
DIB DDEVARCH: Architect Position
Definition at line 2139 of file core_cm33.h.
| #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) |
DIB DDEVARCH: Architect Mask
Definition at line 2140 of file core_cm33.h.
| #define DIB_DDEVARCH_PRESENT_Pos 20U |
DIB DDEVARCH: DEVARCH Present Position
Definition at line 2142 of file core_cm33.h.
| #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) |
DIB DDEVARCH: DEVARCH Present Mask
Definition at line 2143 of file core_cm33.h.
| #define DIB_DDEVARCH_REVISION_Pos 16U |
DIB DDEVARCH: Revision Position
Definition at line 2145 of file core_cm33.h.
| #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) |
DIB DDEVARCH: Revision Mask
Definition at line 2146 of file core_cm33.h.
| #define DIB_DDEVARCH_ARCHVER_Pos 12U |
DIB DDEVARCH: Architecture Version Position
Definition at line 2148 of file core_cm33.h.
| #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) |
DIB DDEVARCH: Architecture Version Mask
Definition at line 2149 of file core_cm33.h.
| #define DIB_DDEVARCH_ARCHPART_Pos 0U |
DIB DDEVARCH: Architecture Part Position
Definition at line 2151 of file core_cm33.h.
| #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) |
DIB DDEVARCH: Architecture Part Mask
Definition at line 2152 of file core_cm33.h.
| #define DIB_DDEVTYPE_SUB_Pos 4U |
DIB DDEVTYPE: Sub-type Position
Definition at line 2155 of file core_cm33.h.
| #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) |
DIB DDEVTYPE: Sub-type Mask
Definition at line 2156 of file core_cm33.h.
| #define DIB_DDEVTYPE_MAJOR_Pos 0U |
DIB DDEVTYPE: Major type Position
Definition at line 2158 of file core_cm33.h.
| #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) |
DIB DDEVTYPE: Major type Mask
Definition at line 2159 of file core_cm33.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 2178 of file core_cm33.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 2186 of file core_cm33.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 2199 of file core_cm33.h.
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
Definition at line 2200 of file core_cm33.h.
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
Definition at line 2201 of file core_cm33.h.
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
Definition at line 2202 of file core_cm33.h.
| #define DCB_BASE (0xE000EDF0UL) |
DCB Base Address
Definition at line 2204 of file core_cm33.h.
| #define DIB_BASE (0xE000EFB0UL) |
DIB Base Address
Definition at line 2205 of file core_cm33.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 2206 of file core_cm33.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 2207 of file core_cm33.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 2208 of file core_cm33.h.
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
Definition at line 2210 of file core_cm33.h.
SCB configuration struct
Definition at line 2211 of file core_cm33.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 2212 of file core_cm33.h.
NVIC configuration struct
Definition at line 2213 of file core_cm33.h.
ITM configuration struct
Definition at line 2214 of file core_cm33.h.
DWT configuration struct
Definition at line 2215 of file core_cm33.h.
TPI configuration struct
Definition at line 2216 of file core_cm33.h.
DCB configuration struct
Definition at line 2218 of file core_cm33.h.
DIB configuration struct
Definition at line 2219 of file core_cm33.h.
| #define MPU_BASE (SCS_BASE + 0x0D90UL) |
Memory Protection Unit
Definition at line 2222 of file core_cm33.h.
Memory Protection Unit
Definition at line 2223 of file core_cm33.h.
| #define FPU_BASE (SCS_BASE + 0x0F30UL) |
Floating Point Unit
Definition at line 2231 of file core_cm33.h.
Floating Point Unit
Definition at line 2232 of file core_cm33.h.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 3201 of file core_cm33.h.
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
Definition at line 488 of file core_cm35p.h.
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
Definition at line 489 of file core_cm35p.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 555 of file core_cm35p.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 556 of file core_cm35p.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 558 of file core_cm35p.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 559 of file core_cm35p.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 561 of file core_cm35p.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 562 of file core_cm35p.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 564 of file core_cm35p.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 565 of file core_cm35p.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 567 of file core_cm35p.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 568 of file core_cm35p.h.
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
Definition at line 571 of file core_cm35p.h.
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
Definition at line 572 of file core_cm35p.h.
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
Definition at line 574 of file core_cm35p.h.
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
Definition at line 575 of file core_cm35p.h.
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
Definition at line 577 of file core_cm35p.h.
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
Definition at line 578 of file core_cm35p.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 580 of file core_cm35p.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 581 of file core_cm35p.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 583 of file core_cm35p.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 584 of file core_cm35p.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 586 of file core_cm35p.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 587 of file core_cm35p.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 589 of file core_cm35p.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 590 of file core_cm35p.h.
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
Definition at line 592 of file core_cm35p.h.
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
Definition at line 593 of file core_cm35p.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 595 of file core_cm35p.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 596 of file core_cm35p.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 598 of file core_cm35p.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 599 of file core_cm35p.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 601 of file core_cm35p.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 602 of file core_cm35p.h.
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
Definition at line 604 of file core_cm35p.h.
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
Definition at line 605 of file core_cm35p.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 607 of file core_cm35p.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 608 of file core_cm35p.h.
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
Definition at line 611 of file core_cm35p.h.
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
Definition at line 612 of file core_cm35p.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 615 of file core_cm35p.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 616 of file core_cm35p.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 618 of file core_cm35p.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 619 of file core_cm35p.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 621 of file core_cm35p.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 622 of file core_cm35p.h.
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
Definition at line 624 of file core_cm35p.h.
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
Definition at line 625 of file core_cm35p.h.
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
Definition at line 627 of file core_cm35p.h.
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
Definition at line 628 of file core_cm35p.h.
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
Definition at line 630 of file core_cm35p.h.
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
Definition at line 631 of file core_cm35p.h.
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
Definition at line 633 of file core_cm35p.h.
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
Definition at line 634 of file core_cm35p.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 636 of file core_cm35p.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 637 of file core_cm35p.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 639 of file core_cm35p.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 640 of file core_cm35p.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 643 of file core_cm35p.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 644 of file core_cm35p.h.
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
Definition at line 646 of file core_cm35p.h.
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
Definition at line 647 of file core_cm35p.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 649 of file core_cm35p.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 650 of file core_cm35p.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 652 of file core_cm35p.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 653 of file core_cm35p.h.
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
SCB CCR: Branch prediction enable bit Position
Definition at line 656 of file core_cm35p.h.
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
SCB CCR: Branch prediction enable bit Mask
Definition at line 657 of file core_cm35p.h.
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
SCB CCR: Instruction cache enable bit Position
Definition at line 659 of file core_cm35p.h.
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
SCB CCR: Instruction cache enable bit Mask
Definition at line 660 of file core_cm35p.h.
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
SCB CCR: Cache enable bit Position
Definition at line 662 of file core_cm35p.h.
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
Definition at line 665 of file core_cm35p.h.
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
Definition at line 666 of file core_cm35p.h.
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
Definition at line 668 of file core_cm35p.h.
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
Definition at line 669 of file core_cm35p.h.
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
Definition at line 671 of file core_cm35p.h.
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
Definition at line 672 of file core_cm35p.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 674 of file core_cm35p.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 675 of file core_cm35p.h.
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
Definition at line 677 of file core_cm35p.h.
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
Definition at line 678 of file core_cm35p.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
Definition at line 681 of file core_cm35p.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
Definition at line 682 of file core_cm35p.h.
| #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
SCB SHCSR: SECUREFAULTPENDED Position
Definition at line 684 of file core_cm35p.h.
| #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
SCB SHCSR: SECUREFAULTPENDED Mask
Definition at line 685 of file core_cm35p.h.
| #define SCB_SHCSR_SECUREFAULTENA_Pos 19U |
SCB SHCSR: SECUREFAULTENA Position
Definition at line 687 of file core_cm35p.h.
| #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
SCB SHCSR: SECUREFAULTENA Mask
Definition at line 688 of file core_cm35p.h.
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
Definition at line 690 of file core_cm35p.h.
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
Definition at line 691 of file core_cm35p.h.
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
Definition at line 693 of file core_cm35p.h.
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
Definition at line 694 of file core_cm35p.h.
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
Definition at line 696 of file core_cm35p.h.
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
Definition at line 697 of file core_cm35p.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 699 of file core_cm35p.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 700 of file core_cm35p.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
Definition at line 702 of file core_cm35p.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
Definition at line 703 of file core_cm35p.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
Definition at line 705 of file core_cm35p.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
Definition at line 706 of file core_cm35p.h.
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
Definition at line 708 of file core_cm35p.h.
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
Definition at line 709 of file core_cm35p.h.
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
Definition at line 711 of file core_cm35p.h.
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
Definition at line 712 of file core_cm35p.h.
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
Definition at line 714 of file core_cm35p.h.
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
Definition at line 715 of file core_cm35p.h.
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
Definition at line 717 of file core_cm35p.h.
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
Definition at line 718 of file core_cm35p.h.
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
Definition at line 720 of file core_cm35p.h.
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
Definition at line 721 of file core_cm35p.h.
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
Definition at line 723 of file core_cm35p.h.
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
Definition at line 724 of file core_cm35p.h.
| #define SCB_SHCSR_SECUREFAULTACT_Pos 4U |
SCB SHCSR: SECUREFAULTACT Position
Definition at line 726 of file core_cm35p.h.
| #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
SCB SHCSR: SECUREFAULTACT Mask
Definition at line 727 of file core_cm35p.h.
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
Definition at line 729 of file core_cm35p.h.
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
Definition at line 730 of file core_cm35p.h.
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
Definition at line 732 of file core_cm35p.h.
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
Definition at line 733 of file core_cm35p.h.
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
Definition at line 735 of file core_cm35p.h.
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
Definition at line 736 of file core_cm35p.h.
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
Definition at line 738 of file core_cm35p.h.
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
Definition at line 739 of file core_cm35p.h.
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
Definition at line 742 of file core_cm35p.h.
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
Definition at line 743 of file core_cm35p.h.
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
Definition at line 745 of file core_cm35p.h.
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
Definition at line 746 of file core_cm35p.h.
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
Definition at line 748 of file core_cm35p.h.
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
Definition at line 749 of file core_cm35p.h.
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
Definition at line 752 of file core_cm35p.h.
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
Definition at line 753 of file core_cm35p.h.
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
Definition at line 755 of file core_cm35p.h.
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
Definition at line 756 of file core_cm35p.h.
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
Definition at line 758 of file core_cm35p.h.
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
Definition at line 759 of file core_cm35p.h.
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
Definition at line 761 of file core_cm35p.h.
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
Definition at line 762 of file core_cm35p.h.
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
Definition at line 764 of file core_cm35p.h.
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
Definition at line 765 of file core_cm35p.h.
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
Definition at line 767 of file core_cm35p.h.
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
Definition at line 768 of file core_cm35p.h.
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
Definition at line 771 of file core_cm35p.h.
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
Definition at line 772 of file core_cm35p.h.
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
Definition at line 774 of file core_cm35p.h.
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
Definition at line 775 of file core_cm35p.h.
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
Definition at line 777 of file core_cm35p.h.
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
Definition at line 778 of file core_cm35p.h.
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
Definition at line 780 of file core_cm35p.h.
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
Definition at line 781 of file core_cm35p.h.
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
Definition at line 783 of file core_cm35p.h.
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
Definition at line 784 of file core_cm35p.h.
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
Definition at line 786 of file core_cm35p.h.
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
Definition at line 787 of file core_cm35p.h.
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
Definition at line 789 of file core_cm35p.h.
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
Definition at line 790 of file core_cm35p.h.
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
Definition at line 793 of file core_cm35p.h.
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
Definition at line 794 of file core_cm35p.h.
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
Definition at line 796 of file core_cm35p.h.
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
Definition at line 797 of file core_cm35p.h.
| #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
SCB CFSR (UFSR): STKOF Position
Definition at line 799 of file core_cm35p.h.
| #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
SCB CFSR (UFSR): STKOF Mask
Definition at line 800 of file core_cm35p.h.
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
Definition at line 802 of file core_cm35p.h.
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
Definition at line 803 of file core_cm35p.h.
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
Definition at line 805 of file core_cm35p.h.
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
Definition at line 806 of file core_cm35p.h.
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
Definition at line 808 of file core_cm35p.h.
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
Definition at line 809 of file core_cm35p.h.
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
Definition at line 811 of file core_cm35p.h.
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
Definition at line 812 of file core_cm35p.h.
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
Definition at line 815 of file core_cm35p.h.
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
Definition at line 816 of file core_cm35p.h.
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
Definition at line 818 of file core_cm35p.h.
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
Definition at line 819 of file core_cm35p.h.
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
Definition at line 821 of file core_cm35p.h.
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
Definition at line 822 of file core_cm35p.h.
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
Definition at line 825 of file core_cm35p.h.
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
Definition at line 826 of file core_cm35p.h.
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
Definition at line 828 of file core_cm35p.h.
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
Definition at line 829 of file core_cm35p.h.
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
Definition at line 831 of file core_cm35p.h.
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
Definition at line 832 of file core_cm35p.h.
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
Definition at line 834 of file core_cm35p.h.
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
Definition at line 835 of file core_cm35p.h.
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
Definition at line 837 of file core_cm35p.h.
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
Definition at line 838 of file core_cm35p.h.
| #define SCB_NSACR_CP11_Pos 11U |
SCB NSACR: CP11 Position
Definition at line 841 of file core_cm35p.h.
| #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
SCB NSACR: CP11 Mask
Definition at line 842 of file core_cm35p.h.
| #define SCB_NSACR_CP10_Pos 10U |
SCB NSACR: CP10 Position
Definition at line 844 of file core_cm35p.h.
| #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
SCB NSACR: CP10 Mask
Definition at line 845 of file core_cm35p.h.
| #define SCB_NSACR_CPn_Pos 0U |
SCB NSACR: CPn Position
Definition at line 847 of file core_cm35p.h.
| #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) |
SCB NSACR: CPn Mask
Definition at line 848 of file core_cm35p.h.
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
Definition at line 851 of file core_cm35p.h.
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
Definition at line 852 of file core_cm35p.h.
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
Definition at line 854 of file core_cm35p.h.
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
Definition at line 855 of file core_cm35p.h.
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
Definition at line 858 of file core_cm35p.h.
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
Definition at line 859 of file core_cm35p.h.
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
Definition at line 861 of file core_cm35p.h.
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
Definition at line 862 of file core_cm35p.h.
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
Definition at line 864 of file core_cm35p.h.
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
Definition at line 865 of file core_cm35p.h.
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
Definition at line 867 of file core_cm35p.h.
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
Definition at line 868 of file core_cm35p.h.
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
Definition at line 870 of file core_cm35p.h.
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
Definition at line 871 of file core_cm35p.h.
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
Definition at line 874 of file core_cm35p.h.
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
Definition at line 875 of file core_cm35p.h.
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
Definition at line 877 of file core_cm35p.h.
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
Definition at line 878 of file core_cm35p.h.
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
Definition at line 880 of file core_cm35p.h.
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
Definition at line 881 of file core_cm35p.h.
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
Definition at line 883 of file core_cm35p.h.
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
Definition at line 884 of file core_cm35p.h.
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
Definition at line 886 of file core_cm35p.h.
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
Definition at line 887 of file core_cm35p.h.
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
Definition at line 889 of file core_cm35p.h.
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
Definition at line 890 of file core_cm35p.h.
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
Definition at line 892 of file core_cm35p.h.
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
Definition at line 893 of file core_cm35p.h.
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
Definition at line 896 of file core_cm35p.h.
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
Definition at line 897 of file core_cm35p.h.
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
Definition at line 899 of file core_cm35p.h.
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
Definition at line 900 of file core_cm35p.h.
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
Definition at line 903 of file core_cm35p.h.
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
Definition at line 904 of file core_cm35p.h.
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
Definition at line 907 of file core_cm35p.h.
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
Definition at line 908 of file core_cm35p.h.
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
Definition at line 910 of file core_cm35p.h.
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
Definition at line 911 of file core_cm35p.h.
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
Definition at line 914 of file core_cm35p.h.
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
Definition at line 915 of file core_cm35p.h.
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
Definition at line 917 of file core_cm35p.h.
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
Definition at line 918 of file core_cm35p.h.
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
Definition at line 921 of file core_cm35p.h.
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
Definition at line 922 of file core_cm35p.h.
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
Definition at line 924 of file core_cm35p.h.
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
Definition at line 925 of file core_cm35p.h.
| #define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
Definition at line 949 of file core_cm35p.h.
| #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
Definition at line 950 of file core_cm35p.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 974 of file core_cm35p.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 975 of file core_cm35p.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 977 of file core_cm35p.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 978 of file core_cm35p.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 980 of file core_cm35p.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 981 of file core_cm35p.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 983 of file core_cm35p.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 984 of file core_cm35p.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 987 of file core_cm35p.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 988 of file core_cm35p.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 991 of file core_cm35p.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 992 of file core_cm35p.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 995 of file core_cm35p.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 996 of file core_cm35p.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 998 of file core_cm35p.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 999 of file core_cm35p.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 1001 of file core_cm35p.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 1002 of file core_cm35p.h.
| #define ITM_STIM_DISABLED_Pos 1U |
ITM STIM: DISABLED Position
Definition at line 1053 of file core_cm35p.h.
| #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) |
ITM STIM: DISABLED Mask
Definition at line 1054 of file core_cm35p.h.
| #define ITM_STIM_FIFOREADY_Pos 0U |
ITM STIM: FIFOREADY Position
Definition at line 1056 of file core_cm35p.h.
| #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) |
ITM STIM: FIFOREADY Mask
Definition at line 1057 of file core_cm35p.h.
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
Definition at line 1060 of file core_cm35p.h.
| #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
Definition at line 1061 of file core_cm35p.h.
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
Definition at line 1064 of file core_cm35p.h.
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
Definition at line 1065 of file core_cm35p.h.
| #define ITM_TCR_TRACEBUSID_Pos 16U |
ITM TCR: ATBID Position
Definition at line 1067 of file core_cm35p.h.
| #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) |
ITM TCR: ATBID Mask
Definition at line 1068 of file core_cm35p.h.
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
Definition at line 1070 of file core_cm35p.h.
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
Definition at line 1071 of file core_cm35p.h.
| #define ITM_TCR_TSPRESCALE_Pos 8U |
ITM TCR: TSPRESCALE Position
Definition at line 1073 of file core_cm35p.h.
| #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) |
ITM TCR: TSPRESCALE Mask
Definition at line 1074 of file core_cm35p.h.
| #define ITM_TCR_STALLENA_Pos 5U |
ITM TCR: STALLENA Position
Definition at line 1076 of file core_cm35p.h.
| #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) |
ITM TCR: STALLENA Mask
Definition at line 1077 of file core_cm35p.h.
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
Definition at line 1079 of file core_cm35p.h.
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
Definition at line 1080 of file core_cm35p.h.
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
Definition at line 1082 of file core_cm35p.h.
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
Definition at line 1083 of file core_cm35p.h.
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
Definition at line 1085 of file core_cm35p.h.
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
Definition at line 1086 of file core_cm35p.h.
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
Definition at line 1088 of file core_cm35p.h.
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
Definition at line 1089 of file core_cm35p.h.
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
Definition at line 1091 of file core_cm35p.h.
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
Definition at line 1092 of file core_cm35p.h.
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
Definition at line 1095 of file core_cm35p.h.
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
Definition at line 1096 of file core_cm35p.h.
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
Definition at line 1098 of file core_cm35p.h.
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
Definition at line 1099 of file core_cm35p.h.
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
Definition at line 1101 of file core_cm35p.h.
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
Definition at line 1102 of file core_cm35p.h.
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
Definition at line 1197 of file core_cm35p.h.
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
Definition at line 1198 of file core_cm35p.h.
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
Definition at line 1200 of file core_cm35p.h.
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
Definition at line 1201 of file core_cm35p.h.
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
Definition at line 1203 of file core_cm35p.h.
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
Definition at line 1204 of file core_cm35p.h.
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
Definition at line 1206 of file core_cm35p.h.
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
Definition at line 1207 of file core_cm35p.h.
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
Definition at line 1209 of file core_cm35p.h.
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
Definition at line 1210 of file core_cm35p.h.
| #define DWT_CTRL_CYCDISS_Pos 23U |
DWT CTRL: CYCDISS Position
Definition at line 1212 of file core_cm35p.h.
| #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) |
DWT CTRL: CYCDISS Mask
Definition at line 1213 of file core_cm35p.h.
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
Definition at line 1215 of file core_cm35p.h.
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
Definition at line 1216 of file core_cm35p.h.
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
Definition at line 1218 of file core_cm35p.h.
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
Definition at line 1219 of file core_cm35p.h.
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
Definition at line 1221 of file core_cm35p.h.
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
Definition at line 1222 of file core_cm35p.h.
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
Definition at line 1224 of file core_cm35p.h.
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
Definition at line 1225 of file core_cm35p.h.
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
Definition at line 1227 of file core_cm35p.h.
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
Definition at line 1228 of file core_cm35p.h.
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
Definition at line 1230 of file core_cm35p.h.
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
Definition at line 1231 of file core_cm35p.h.
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
Definition at line 1233 of file core_cm35p.h.
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
Definition at line 1234 of file core_cm35p.h.
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
Definition at line 1236 of file core_cm35p.h.
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
Definition at line 1237 of file core_cm35p.h.
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
Definition at line 1239 of file core_cm35p.h.
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
Definition at line 1240 of file core_cm35p.h.
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
Definition at line 1242 of file core_cm35p.h.
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
Definition at line 1243 of file core_cm35p.h.
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
Definition at line 1245 of file core_cm35p.h.
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
Definition at line 1246 of file core_cm35p.h.
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
Definition at line 1248 of file core_cm35p.h.
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
Definition at line 1249 of file core_cm35p.h.
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
Definition at line 1251 of file core_cm35p.h.
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
Definition at line 1252 of file core_cm35p.h.
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
Definition at line 1255 of file core_cm35p.h.
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
Definition at line 1256 of file core_cm35p.h.
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
Definition at line 1259 of file core_cm35p.h.
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
Definition at line 1260 of file core_cm35p.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
Definition at line 1263 of file core_cm35p.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
Definition at line 1264 of file core_cm35p.h.
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
Definition at line 1267 of file core_cm35p.h.
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
Definition at line 1268 of file core_cm35p.h.
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
Definition at line 1271 of file core_cm35p.h.
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
Definition at line 1272 of file core_cm35p.h.
| #define DWT_FUNCTION_ID_Pos 27U |
DWT FUNCTION: ID Position
Definition at line 1275 of file core_cm35p.h.
| #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) |
DWT FUNCTION: ID Mask
Definition at line 1276 of file core_cm35p.h.
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
Definition at line 1278 of file core_cm35p.h.
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
Definition at line 1279 of file core_cm35p.h.
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
Definition at line 1281 of file core_cm35p.h.
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
Definition at line 1282 of file core_cm35p.h.
| #define DWT_FUNCTION_ACTION_Pos 4U |
DWT FUNCTION: ACTION Position
Definition at line 1284 of file core_cm35p.h.
| #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) |
DWT FUNCTION: ACTION Mask
Definition at line 1285 of file core_cm35p.h.
| #define DWT_FUNCTION_MATCH_Pos 0U |
DWT FUNCTION: MATCH Position
Definition at line 1287 of file core_cm35p.h.
| #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) |
DWT FUNCTION: MATCH Mask
Definition at line 1288 of file core_cm35p.h.
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
Definition at line 1332 of file core_cm35p.h.
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
Definition at line 1333 of file core_cm35p.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 1336 of file core_cm35p.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 1337 of file core_cm35p.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 1340 of file core_cm35p.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 1341 of file core_cm35p.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 1343 of file core_cm35p.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 1344 of file core_cm35p.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 1346 of file core_cm35p.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 1347 of file core_cm35p.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 1349 of file core_cm35p.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 1350 of file core_cm35p.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 1353 of file core_cm35p.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 1354 of file core_cm35p.h.
| #define TPI_FFCR_FOnMan_Pos 6U |
TPI FFCR: FOnMan Position
Definition at line 1356 of file core_cm35p.h.
| #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) |
TPI FFCR: FOnMan Mask
Definition at line 1357 of file core_cm35p.h.
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
Definition at line 1359 of file core_cm35p.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 1360 of file core_cm35p.h.
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
Definition at line 1363 of file core_cm35p.h.
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
Definition at line 1364 of file core_cm35p.h.
| #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U |
TPI ITFTTD0: ATB Interface 2 ATVALIDPosition
Definition at line 1367 of file core_cm35p.h.
| #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) |
TPI ITFTTD0: ATB Interface 2 ATVALID Mask
Definition at line 1368 of file core_cm35p.h.
| #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U |
TPI ITFTTD0: ATB Interface 2 byte count Position
Definition at line 1370 of file core_cm35p.h.
| #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) |
TPI ITFTTD0: ATB Interface 2 byte count Mask
Definition at line 1371 of file core_cm35p.h.
| #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U |
TPI ITFTTD0: ATB Interface 1 ATVALID Position
Definition at line 1373 of file core_cm35p.h.
| #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) |
TPI ITFTTD0: ATB Interface 1 ATVALID Mask
Definition at line 1374 of file core_cm35p.h.
| #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U |
TPI ITFTTD0: ATB Interface 1 byte count Position
Definition at line 1376 of file core_cm35p.h.
| #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) |
TPI ITFTTD0: ATB Interface 1 byte countt Mask
Definition at line 1377 of file core_cm35p.h.
| #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U |
TPI ITFTTD0: ATB Interface 1 data2 Position
Definition at line 1379 of file core_cm35p.h.
| #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) |
TPI ITFTTD0: ATB Interface 1 data2 Mask
Definition at line 1380 of file core_cm35p.h.
| #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U |
TPI ITFTTD0: ATB Interface 1 data1 Position
Definition at line 1382 of file core_cm35p.h.
| #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) |
TPI ITFTTD0: ATB Interface 1 data1 Mask
Definition at line 1383 of file core_cm35p.h.
| #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U |
TPI ITFTTD0: ATB Interface 1 data0 Position
Definition at line 1385 of file core_cm35p.h.
| #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) |
TPI ITFTTD0: ATB Interface 1 data0 Mask
Definition at line 1386 of file core_cm35p.h.
| #define TPI_ITATBCTR2_AFVALID2S_Pos 1U |
TPI ITATBCTR2: AFVALID2S Position
Definition at line 1389 of file core_cm35p.h.
| #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) |
TPI ITATBCTR2: AFVALID2SS Mask
Definition at line 1390 of file core_cm35p.h.
| #define TPI_ITATBCTR2_AFVALID1S_Pos 1U |
TPI ITATBCTR2: AFVALID1S Position
Definition at line 1392 of file core_cm35p.h.
| #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) |
TPI ITATBCTR2: AFVALID1SS Mask
Definition at line 1393 of file core_cm35p.h.
| #define TPI_ITATBCTR2_ATREADY2S_Pos 0U |
TPI ITATBCTR2: ATREADY2S Position
Definition at line 1395 of file core_cm35p.h.
| #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) |
TPI ITATBCTR2: ATREADY2S Mask
Definition at line 1396 of file core_cm35p.h.
| #define TPI_ITATBCTR2_ATREADY1S_Pos 0U |
TPI ITATBCTR2: ATREADY1S Position
Definition at line 1398 of file core_cm35p.h.
| #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) |
TPI ITATBCTR2: ATREADY1S Mask
Definition at line 1399 of file core_cm35p.h.
| #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U |
TPI ITFTTD1: ATB Interface 2 ATVALID Position
Definition at line 1402 of file core_cm35p.h.
| #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) |
TPI ITFTTD1: ATB Interface 2 ATVALID Mask
Definition at line 1403 of file core_cm35p.h.
| #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U |
TPI ITFTTD1: ATB Interface 2 byte count Position
Definition at line 1405 of file core_cm35p.h.
| #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) |
TPI ITFTTD1: ATB Interface 2 byte count Mask
Definition at line 1406 of file core_cm35p.h.
| #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U |
TPI ITFTTD1: ATB Interface 1 ATVALID Position
Definition at line 1408 of file core_cm35p.h.
| #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) |
TPI ITFTTD1: ATB Interface 1 ATVALID Mask
Definition at line 1409 of file core_cm35p.h.
| #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U |
TPI ITFTTD1: ATB Interface 1 byte count Position
Definition at line 1411 of file core_cm35p.h.
| #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) |
TPI ITFTTD1: ATB Interface 1 byte countt Mask
Definition at line 1412 of file core_cm35p.h.
| #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U |
TPI ITFTTD1: ATB Interface 2 data2 Position
Definition at line 1414 of file core_cm35p.h.
| #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) |
TPI ITFTTD1: ATB Interface 2 data2 Mask
Definition at line 1415 of file core_cm35p.h.
| #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U |
TPI ITFTTD1: ATB Interface 2 data1 Position
Definition at line 1417 of file core_cm35p.h.
| #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) |
TPI ITFTTD1: ATB Interface 2 data1 Mask
Definition at line 1418 of file core_cm35p.h.
| #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U |
TPI ITFTTD1: ATB Interface 2 data0 Position
Definition at line 1420 of file core_cm35p.h.
| #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) |
TPI ITFTTD1: ATB Interface 2 data0 Mask
Definition at line 1421 of file core_cm35p.h.
| #define TPI_ITATBCTR0_AFVALID2S_Pos 1U |
TPI ITATBCTR0: AFVALID2S Position
Definition at line 1424 of file core_cm35p.h.
| #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) |
TPI ITATBCTR0: AFVALID2SS Mask
Definition at line 1425 of file core_cm35p.h.
| #define TPI_ITATBCTR0_AFVALID1S_Pos 1U |
TPI ITATBCTR0: AFVALID1S Position
Definition at line 1427 of file core_cm35p.h.
| #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) |
TPI ITATBCTR0: AFVALID1SS Mask
Definition at line 1428 of file core_cm35p.h.
| #define TPI_ITATBCTR0_ATREADY2S_Pos 0U |
TPI ITATBCTR0: ATREADY2S Position
Definition at line 1430 of file core_cm35p.h.
| #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) |
TPI ITATBCTR0: ATREADY2S Mask
Definition at line 1431 of file core_cm35p.h.
| #define TPI_ITATBCTR0_ATREADY1S_Pos 0U |
TPI ITATBCTR0: ATREADY1S Position
Definition at line 1433 of file core_cm35p.h.
| #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) |
TPI ITATBCTR0: ATREADY1S Mask
Definition at line 1434 of file core_cm35p.h.
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
Definition at line 1437 of file core_cm35p.h.
| #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
Definition at line 1438 of file core_cm35p.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 1441 of file core_cm35p.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1442 of file core_cm35p.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 1444 of file core_cm35p.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1445 of file core_cm35p.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 1447 of file core_cm35p.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1448 of file core_cm35p.h.
| #define TPI_DEVID_FIFOSZ_Pos 6U |
TPI DEVID: FIFOSZ Position
TPI DEVID: FIFO depth Position
Definition at line 1450 of file core_cm35p.h.
| #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) |
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
Definition at line 1453 of file core_cm35p.h.
| #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
Definition at line 1454 of file core_cm35p.h.
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
Definition at line 1457 of file core_cm35p.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 1458 of file core_cm35p.h.
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
Definition at line 1460 of file core_cm35p.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1461 of file core_cm35p.h.
| #define MPU_TYPE_IREGION_Pos 16U |
MPU TYPE: IREGION Position
Definition at line 1503 of file core_cm35p.h.
| #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) |
MPU TYPE: IREGION Mask
Definition at line 1504 of file core_cm35p.h.
| #define MPU_TYPE_DREGION_Pos 8U |
MPU TYPE: DREGION Position
Definition at line 1506 of file core_cm35p.h.
| #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) |
MPU TYPE: DREGION Mask
Definition at line 1507 of file core_cm35p.h.
| #define MPU_TYPE_SEPARATE_Pos 0U |
MPU TYPE: SEPARATE Position
Definition at line 1509 of file core_cm35p.h.
| #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) |
MPU TYPE: SEPARATE Mask
Definition at line 1510 of file core_cm35p.h.
| #define MPU_CTRL_PRIVDEFENA_Pos 2U |
MPU CTRL: PRIVDEFENA Position
Definition at line 1513 of file core_cm35p.h.
| #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) |
MPU CTRL: PRIVDEFENA Mask
Definition at line 1514 of file core_cm35p.h.
| #define MPU_CTRL_HFNMIENA_Pos 1U |
MPU CTRL: HFNMIENA Position
Definition at line 1516 of file core_cm35p.h.
| #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) |
MPU CTRL: HFNMIENA Mask
Definition at line 1517 of file core_cm35p.h.
| #define MPU_CTRL_ENABLE_Pos 0U |
MPU CTRL: ENABLE Position
Definition at line 1519 of file core_cm35p.h.
| #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) |
MPU CTRL: ENABLE Mask
Definition at line 1520 of file core_cm35p.h.
| #define MPU_RNR_REGION_Pos 0U |
MPU RNR: REGION Position
Definition at line 1523 of file core_cm35p.h.
| #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) |
MPU RNR: REGION Mask
Definition at line 1524 of file core_cm35p.h.
| #define MPU_RBAR_BASE_Pos 5U |
MPU RBAR: BASE Position
Definition at line 1527 of file core_cm35p.h.
| #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) |
MPU RBAR: BASE Mask
Definition at line 1528 of file core_cm35p.h.
| #define MPU_RBAR_SH_Pos 3U |
MPU RBAR: SH Position
Definition at line 1530 of file core_cm35p.h.
| #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) |
MPU RBAR: SH Mask
Definition at line 1531 of file core_cm35p.h.
| #define MPU_RBAR_AP_Pos 1U |
MPU RBAR: AP Position
Definition at line 1533 of file core_cm35p.h.
| #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) |
MPU RBAR: AP Mask
Definition at line 1534 of file core_cm35p.h.
| #define MPU_RBAR_XN_Pos 0U |
MPU RBAR: XN Position
Definition at line 1536 of file core_cm35p.h.
| #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) |
MPU RBAR: XN Mask
Definition at line 1537 of file core_cm35p.h.
| #define MPU_RLAR_LIMIT_Pos 5U |
MPU RLAR: LIMIT Position
Definition at line 1540 of file core_cm35p.h.
| #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) |
MPU RLAR: LIMIT Mask
Definition at line 1541 of file core_cm35p.h.
| #define MPU_RLAR_AttrIndx_Pos 1U |
MPU RLAR: AttrIndx Position
Definition at line 1543 of file core_cm35p.h.
| #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) |
MPU RLAR: AttrIndx Mask
Definition at line 1544 of file core_cm35p.h.
| #define MPU_RLAR_EN_Pos 0U |
MPU RLAR: Region enable bit Position
Definition at line 1546 of file core_cm35p.h.
| #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) |
MPU RLAR: Region enable bit Disable Mask
Definition at line 1547 of file core_cm35p.h.
| #define MPU_MAIR0_Attr3_Pos 24U |
MPU MAIR0: Attr3 Position
Definition at line 1550 of file core_cm35p.h.
| #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) |
MPU MAIR0: Attr3 Mask
Definition at line 1551 of file core_cm35p.h.
| #define MPU_MAIR0_Attr2_Pos 16U |
MPU MAIR0: Attr2 Position
Definition at line 1553 of file core_cm35p.h.
| #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) |
MPU MAIR0: Attr2 Mask
Definition at line 1554 of file core_cm35p.h.
| #define MPU_MAIR0_Attr1_Pos 8U |
MPU MAIR0: Attr1 Position
Definition at line 1556 of file core_cm35p.h.
| #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) |
MPU MAIR0: Attr1 Mask
Definition at line 1557 of file core_cm35p.h.
| #define MPU_MAIR0_Attr0_Pos 0U |
MPU MAIR0: Attr0 Position
Definition at line 1559 of file core_cm35p.h.
| #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) |
MPU MAIR0: Attr0 Mask
Definition at line 1560 of file core_cm35p.h.
| #define MPU_MAIR1_Attr7_Pos 24U |
MPU MAIR1: Attr7 Position
Definition at line 1563 of file core_cm35p.h.
| #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) |
MPU MAIR1: Attr7 Mask
Definition at line 1564 of file core_cm35p.h.
| #define MPU_MAIR1_Attr6_Pos 16U |
MPU MAIR1: Attr6 Position
Definition at line 1566 of file core_cm35p.h.
| #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) |
MPU MAIR1: Attr6 Mask
Definition at line 1567 of file core_cm35p.h.
| #define MPU_MAIR1_Attr5_Pos 8U |
MPU MAIR1: Attr5 Position
Definition at line 1569 of file core_cm35p.h.
| #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) |
MPU MAIR1: Attr5 Mask
Definition at line 1570 of file core_cm35p.h.
| #define MPU_MAIR1_Attr4_Pos 0U |
MPU MAIR1: Attr4 Position
Definition at line 1572 of file core_cm35p.h.
| #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) |
MPU MAIR1: Attr4 Mask
Definition at line 1573 of file core_cm35p.h.
| #define FPU_FPCCR_ASPEN_Pos 31U |
FPCCR: ASPEN bit Position
Definition at line 1688 of file core_cm35p.h.
| #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) |
FPCCR: ASPEN bit Mask
Definition at line 1689 of file core_cm35p.h.
| #define FPU_FPCCR_LSPEN_Pos 30U |
FPCCR: LSPEN Position
Definition at line 1691 of file core_cm35p.h.
| #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) |
FPCCR: LSPEN bit Mask
Definition at line 1692 of file core_cm35p.h.
| #define FPU_FPCCR_LSPENS_Pos 29U |
FPCCR: LSPENS Position
Definition at line 1694 of file core_cm35p.h.
| #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) |
FPCCR: LSPENS bit Mask
Definition at line 1695 of file core_cm35p.h.
| #define FPU_FPCCR_CLRONRET_Pos 28U |
FPCCR: CLRONRET Position
Definition at line 1697 of file core_cm35p.h.
| #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) |
FPCCR: CLRONRET bit Mask
Definition at line 1698 of file core_cm35p.h.
| #define FPU_FPCCR_CLRONRETS_Pos 27U |
FPCCR: CLRONRETS Position
Definition at line 1700 of file core_cm35p.h.
| #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) |
FPCCR: CLRONRETS bit Mask
Definition at line 1701 of file core_cm35p.h.
| #define FPU_FPCCR_TS_Pos 26U |
FPCCR: TS Position
Definition at line 1703 of file core_cm35p.h.
| #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) |
FPCCR: TS bit Mask
Definition at line 1704 of file core_cm35p.h.
| #define FPU_FPCCR_UFRDY_Pos 10U |
FPCCR: UFRDY Position
Definition at line 1706 of file core_cm35p.h.
| #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) |
FPCCR: UFRDY bit Mask
Definition at line 1707 of file core_cm35p.h.
| #define FPU_FPCCR_SPLIMVIOL_Pos 9U |
FPCCR: SPLIMVIOL Position
Definition at line 1709 of file core_cm35p.h.
| #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) |
FPCCR: SPLIMVIOL bit Mask
Definition at line 1710 of file core_cm35p.h.
| #define FPU_FPCCR_MONRDY_Pos 8U |
FPCCR: MONRDY Position
Definition at line 1712 of file core_cm35p.h.
| #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) |
FPCCR: MONRDY bit Mask
Definition at line 1713 of file core_cm35p.h.
| #define FPU_FPCCR_SFRDY_Pos 7U |
FPCCR: SFRDY Position
Definition at line 1715 of file core_cm35p.h.
| #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) |
FPCCR: SFRDY bit Mask
Definition at line 1716 of file core_cm35p.h.
| #define FPU_FPCCR_BFRDY_Pos 6U |
FPCCR: BFRDY Position
Definition at line 1718 of file core_cm35p.h.
| #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) |
FPCCR: BFRDY bit Mask
Definition at line 1719 of file core_cm35p.h.
| #define FPU_FPCCR_MMRDY_Pos 5U |
FPCCR: MMRDY Position
Definition at line 1721 of file core_cm35p.h.
| #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) |
FPCCR: MMRDY bit Mask
Definition at line 1722 of file core_cm35p.h.
| #define FPU_FPCCR_HFRDY_Pos 4U |
FPCCR: HFRDY Position
Definition at line 1724 of file core_cm35p.h.
| #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) |
FPCCR: HFRDY bit Mask
Definition at line 1725 of file core_cm35p.h.
| #define FPU_FPCCR_THREAD_Pos 3U |
FPCCR: processor mode bit Position
Definition at line 1727 of file core_cm35p.h.
| #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) |
FPCCR: processor mode active bit Mask
Definition at line 1728 of file core_cm35p.h.
| #define FPU_FPCCR_S_Pos 2U |
FPCCR: Security status of the FP context bit Position
Definition at line 1730 of file core_cm35p.h.
| #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) |
FPCCR: Security status of the FP context bit Mask
Definition at line 1731 of file core_cm35p.h.
| #define FPU_FPCCR_USER_Pos 1U |
FPCCR: privilege level bit Position
Definition at line 1733 of file core_cm35p.h.
| #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) |
FPCCR: privilege level bit Mask
Definition at line 1734 of file core_cm35p.h.
| #define FPU_FPCCR_LSPACT_Pos 0U |
FPCCR: Lazy state preservation active bit Position
Definition at line 1736 of file core_cm35p.h.
| #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) |
FPCCR: Lazy state preservation active bit Mask
Definition at line 1737 of file core_cm35p.h.
| #define FPU_FPCAR_ADDRESS_Pos 3U |
FPCAR: ADDRESS bit Position
Definition at line 1740 of file core_cm35p.h.
| #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) |
FPCAR: ADDRESS bit Mask
Definition at line 1741 of file core_cm35p.h.
| #define FPU_FPDSCR_AHP_Pos 26U |
FPDSCR: AHP bit Position
Definition at line 1744 of file core_cm35p.h.
| #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) |
FPDSCR: AHP bit Mask
Definition at line 1745 of file core_cm35p.h.
| #define FPU_FPDSCR_DN_Pos 25U |
FPDSCR: DN bit Position
Definition at line 1747 of file core_cm35p.h.
| #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) |
FPDSCR: DN bit Mask
Definition at line 1748 of file core_cm35p.h.
| #define FPU_FPDSCR_FZ_Pos 24U |
FPDSCR: FZ bit Position
Definition at line 1750 of file core_cm35p.h.
| #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) |
FPDSCR: FZ bit Mask
Definition at line 1751 of file core_cm35p.h.
| #define FPU_FPDSCR_RMode_Pos 22U |
FPDSCR: RMode bit Position
Definition at line 1753 of file core_cm35p.h.
| #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) |
FPDSCR: RMode bit Mask
Definition at line 1754 of file core_cm35p.h.
| #define FPU_MVFR0_FP_rounding_modes_Pos 28U |
MVFR0: FP rounding modes bits Position
Definition at line 1757 of file core_cm35p.h.
| #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) |
MVFR0: FP rounding modes bits Mask
Definition at line 1758 of file core_cm35p.h.
| #define FPU_MVFR0_Short_vectors_Pos 24U |
MVFR0: Short vectors bits Position
Definition at line 1760 of file core_cm35p.h.
| #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) |
MVFR0: Short vectors bits Mask
Definition at line 1761 of file core_cm35p.h.
| #define FPU_MVFR0_Square_root_Pos 20U |
MVFR0: Square root bits Position
Definition at line 1763 of file core_cm35p.h.
| #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) |
MVFR0: Square root bits Mask
Definition at line 1764 of file core_cm35p.h.
| #define FPU_MVFR0_Divide_Pos 16U |
MVFR0: Divide bits Position
Definition at line 1766 of file core_cm35p.h.
| #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) |
MVFR0: Divide bits Mask
Definition at line 1767 of file core_cm35p.h.
| #define FPU_MVFR0_FP_excep_trapping_Pos 12U |
MVFR0: FP exception trapping bits Position
Definition at line 1769 of file core_cm35p.h.
| #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) |
MVFR0: FP exception trapping bits Mask
Definition at line 1770 of file core_cm35p.h.
| #define FPU_MVFR0_Double_precision_Pos 8U |
MVFR0: Double-precision bits Position
Definition at line 1772 of file core_cm35p.h.
| #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) |
MVFR0: Double-precision bits Mask
Definition at line 1773 of file core_cm35p.h.
| #define FPU_MVFR0_Single_precision_Pos 4U |
MVFR0: Single-precision bits Position
Definition at line 1775 of file core_cm35p.h.
| #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) |
MVFR0: Single-precision bits Mask
Definition at line 1776 of file core_cm35p.h.
| #define FPU_MVFR0_A_SIMD_registers_Pos 0U |
MVFR0: A_SIMD registers bits Position
Definition at line 1778 of file core_cm35p.h.
| #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) |
MVFR0: A_SIMD registers bits Mask
Definition at line 1779 of file core_cm35p.h.
| #define FPU_MVFR1_FP_fused_MAC_Pos 28U |
MVFR1: FP fused MAC bits Position
Definition at line 1782 of file core_cm35p.h.
| #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) |
MVFR1: FP fused MAC bits Mask
Definition at line 1783 of file core_cm35p.h.
| #define FPU_MVFR1_FP_HPFP_Pos 24U |
MVFR1: FP HPFP bits Position
Definition at line 1785 of file core_cm35p.h.
| #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) |
MVFR1: FP HPFP bits Mask
Definition at line 1786 of file core_cm35p.h.
| #define FPU_MVFR1_D_NaN_mode_Pos 4U |
MVFR1: D_NaN mode bits Position
Definition at line 1788 of file core_cm35p.h.
| #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) |
MVFR1: D_NaN mode bits Mask
Definition at line 1789 of file core_cm35p.h.
| #define FPU_MVFR1_FtZ_mode_Pos 0U |
MVFR1: FtZ mode bits Position
Definition at line 1791 of file core_cm35p.h.
| #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) |
MVFR1: FtZ mode bits Mask
Definition at line 1792 of file core_cm35p.h.
| #define FPU_MVFR2_FPMisc_Pos 4U |
MVFR2: FPMisc bits Position
Definition at line 1795 of file core_cm35p.h.
| #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) |
MVFR2: FPMisc bits Mask
Definition at line 1796 of file core_cm35p.h.
| #define DCB_DHCSR_DBGKEY_Pos 16U |
DCB DHCSR: Debug key Position
Definition at line 1957 of file core_cm35p.h.
| #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) |
DCB DHCSR: Debug key Mask
Definition at line 1958 of file core_cm35p.h.
| #define DCB_DHCSR_S_RESTART_ST_Pos 26U |
DCB DHCSR: Restart sticky status Position
Definition at line 1960 of file core_cm35p.h.
| #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) |
DCB DHCSR: Restart sticky status Mask
Definition at line 1961 of file core_cm35p.h.
| #define DCB_DHCSR_S_RESET_ST_Pos 25U |
DCB DHCSR: Reset sticky status Position
Definition at line 1963 of file core_cm35p.h.
| #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) |
DCB DHCSR: Reset sticky status Mask
Definition at line 1964 of file core_cm35p.h.
| #define DCB_DHCSR_S_RETIRE_ST_Pos 24U |
DCB DHCSR: Retire sticky status Position
Definition at line 1966 of file core_cm35p.h.
| #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) |
DCB DHCSR: Retire sticky status Mask
Definition at line 1967 of file core_cm35p.h.
| #define DCB_DHCSR_S_SDE_Pos 20U |
DCB DHCSR: Secure debug enabled Position
Definition at line 1969 of file core_cm35p.h.
| #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) |
DCB DHCSR: Secure debug enabled Mask
Definition at line 1970 of file core_cm35p.h.
| #define DCB_DHCSR_S_LOCKUP_Pos 19U |
DCB DHCSR: Lockup status Position
Definition at line 1972 of file core_cm35p.h.
| #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) |
DCB DHCSR: Lockup status Mask
Definition at line 1973 of file core_cm35p.h.
| #define DCB_DHCSR_S_SLEEP_Pos 18U |
DCB DHCSR: Sleeping status Position
Definition at line 1975 of file core_cm35p.h.
| #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) |
DCB DHCSR: Sleeping status Mask
Definition at line 1976 of file core_cm35p.h.
| #define DCB_DHCSR_S_HALT_Pos 17U |
DCB DHCSR: Halted status Position
Definition at line 1978 of file core_cm35p.h.
| #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) |
DCB DHCSR: Halted status Mask
Definition at line 1979 of file core_cm35p.h.
| #define DCB_DHCSR_S_REGRDY_Pos 16U |
DCB DHCSR: Register ready status Position
Definition at line 1981 of file core_cm35p.h.
| #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) |
DCB DHCSR: Register ready status Mask
Definition at line 1982 of file core_cm35p.h.
| #define DCB_DHCSR_C_SNAPSTALL_Pos 5U |
DCB DHCSR: Snap stall control Position
Definition at line 1984 of file core_cm35p.h.
| #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) |
DCB DHCSR: Snap stall control Mask
Definition at line 1985 of file core_cm35p.h.
| #define DCB_DHCSR_C_MASKINTS_Pos 3U |
DCB DHCSR: Mask interrupts control Position
Definition at line 1987 of file core_cm35p.h.
| #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) |
DCB DHCSR: Mask interrupts control Mask
Definition at line 1988 of file core_cm35p.h.
| #define DCB_DHCSR_C_STEP_Pos 2U |
DCB DHCSR: Step control Position
Definition at line 1990 of file core_cm35p.h.
| #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) |
DCB DHCSR: Step control Mask
Definition at line 1991 of file core_cm35p.h.
| #define DCB_DHCSR_C_HALT_Pos 1U |
DCB DHCSR: Halt control Position
Definition at line 1993 of file core_cm35p.h.
| #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) |
DCB DHCSR: Halt control Mask
Definition at line 1994 of file core_cm35p.h.
| #define DCB_DHCSR_C_DEBUGEN_Pos 0U |
DCB DHCSR: Debug enable control Position
Definition at line 1996 of file core_cm35p.h.
| #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) |
DCB DHCSR: Debug enable control Mask
Definition at line 1997 of file core_cm35p.h.
| #define DCB_DCRSR_REGWnR_Pos 16U |
DCB DCRSR: Register write/not-read Position
Definition at line 2000 of file core_cm35p.h.
| #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) |
DCB DCRSR: Register write/not-read Mask
Definition at line 2001 of file core_cm35p.h.
| #define DCB_DCRSR_REGSEL_Pos 0U |
DCB DCRSR: Register selector Position
Definition at line 2003 of file core_cm35p.h.
| #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) |
DCB DCRSR: Register selector Mask
Definition at line 2004 of file core_cm35p.h.
| #define DCB_DCRDR_DBGTMP_Pos 0U |
DCB DCRDR: Data temporary buffer Position
Definition at line 2007 of file core_cm35p.h.
| #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) |
DCB DCRDR: Data temporary buffer Mask
Definition at line 2008 of file core_cm35p.h.
| #define DCB_DEMCR_TRCENA_Pos 24U |
DCB DEMCR: Trace enable Position
Definition at line 2011 of file core_cm35p.h.
| #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) |
DCB DEMCR: Trace enable Mask
Definition at line 2012 of file core_cm35p.h.
| #define DCB_DEMCR_MONPRKEY_Pos 23U |
DCB DEMCR: Monitor pend req key Position
Definition at line 2014 of file core_cm35p.h.
| #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) |
DCB DEMCR: Monitor pend req key Mask
Definition at line 2015 of file core_cm35p.h.
| #define DCB_DEMCR_UMON_EN_Pos 21U |
DCB DEMCR: Unprivileged monitor enable Position
Definition at line 2017 of file core_cm35p.h.
| #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) |
DCB DEMCR: Unprivileged monitor enable Mask
Definition at line 2018 of file core_cm35p.h.
| #define DCB_DEMCR_SDME_Pos 20U |
DCB DEMCR: Secure DebugMonitor enable Position
Definition at line 2020 of file core_cm35p.h.
| #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) |
DCB DEMCR: Secure DebugMonitor enable Mask
Definition at line 2021 of file core_cm35p.h.
| #define DCB_DEMCR_MON_REQ_Pos 19U |
DCB DEMCR: Monitor request Position
Definition at line 2023 of file core_cm35p.h.
| #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) |
DCB DEMCR: Monitor request Mask
Definition at line 2024 of file core_cm35p.h.
| #define DCB_DEMCR_MON_STEP_Pos 18U |
DCB DEMCR: Monitor step Position
Definition at line 2026 of file core_cm35p.h.
| #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) |
DCB DEMCR: Monitor step Mask
Definition at line 2027 of file core_cm35p.h.
| #define DCB_DEMCR_MON_PEND_Pos 17U |
DCB DEMCR: Monitor pend Position
Definition at line 2029 of file core_cm35p.h.
| #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) |
DCB DEMCR: Monitor pend Mask
Definition at line 2030 of file core_cm35p.h.
| #define DCB_DEMCR_MON_EN_Pos 16U |
DCB DEMCR: Monitor enable Position
Definition at line 2032 of file core_cm35p.h.
| #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) |
DCB DEMCR: Monitor enable Mask
Definition at line 2033 of file core_cm35p.h.
| #define DCB_DEMCR_VC_SFERR_Pos 11U |
DCB DEMCR: Vector Catch SecureFault Position
Definition at line 2035 of file core_cm35p.h.
| #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) |
DCB DEMCR: Vector Catch SecureFault Mask
Definition at line 2036 of file core_cm35p.h.
| #define DCB_DEMCR_VC_HARDERR_Pos 10U |
DCB DEMCR: Vector Catch HardFault errors Position
Definition at line 2038 of file core_cm35p.h.
| #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) |
DCB DEMCR: Vector Catch HardFault errors Mask
Definition at line 2039 of file core_cm35p.h.
| #define DCB_DEMCR_VC_INTERR_Pos 9U |
DCB DEMCR: Vector Catch interrupt errors Position
Definition at line 2041 of file core_cm35p.h.
| #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) |
DCB DEMCR: Vector Catch interrupt errors Mask
Definition at line 2042 of file core_cm35p.h.
| #define DCB_DEMCR_VC_BUSERR_Pos 8U |
DCB DEMCR: Vector Catch BusFault errors Position
Definition at line 2044 of file core_cm35p.h.
| #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) |
DCB DEMCR: Vector Catch BusFault errors Mask
Definition at line 2045 of file core_cm35p.h.
| #define DCB_DEMCR_VC_STATERR_Pos 7U |
DCB DEMCR: Vector Catch state errors Position
Definition at line 2047 of file core_cm35p.h.
| #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) |
DCB DEMCR: Vector Catch state errors Mask
Definition at line 2048 of file core_cm35p.h.
| #define DCB_DEMCR_VC_CHKERR_Pos 6U |
DCB DEMCR: Vector Catch check errors Position
Definition at line 2050 of file core_cm35p.h.
| #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) |
DCB DEMCR: Vector Catch check errors Mask
Definition at line 2051 of file core_cm35p.h.
| #define DCB_DEMCR_VC_NOCPERR_Pos 5U |
DCB DEMCR: Vector Catch NOCP errors Position
Definition at line 2053 of file core_cm35p.h.
| #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) |
DCB DEMCR: Vector Catch NOCP errors Mask
Definition at line 2054 of file core_cm35p.h.
| #define DCB_DEMCR_VC_MMERR_Pos 4U |
DCB DEMCR: Vector Catch MemManage errors Position
Definition at line 2056 of file core_cm35p.h.
| #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) |
DCB DEMCR: Vector Catch MemManage errors Mask
Definition at line 2057 of file core_cm35p.h.
| #define DCB_DEMCR_VC_CORERESET_Pos 0U |
DCB DEMCR: Vector Catch Core reset Position
Definition at line 2059 of file core_cm35p.h.
| #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) |
DCB DEMCR: Vector Catch Core reset Mask
Definition at line 2060 of file core_cm35p.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position
Definition at line 2063 of file core_cm35p.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask
Definition at line 2064 of file core_cm35p.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U |
DCB DAUTHCTRL: Secure non-invasive debug enable select Position
Definition at line 2066 of file core_cm35p.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) |
DCB DAUTHCTRL: Secure non-invasive debug enable select Mask
Definition at line 2067 of file core_cm35p.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U |
DCB DAUTHCTRL: Internal Secure invasive debug enable Position
Definition at line 2069 of file core_cm35p.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure invasive debug enable Mask
Definition at line 2070 of file core_cm35p.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U |
DCB DAUTHCTRL: Secure invasive debug enable select Position
Definition at line 2072 of file core_cm35p.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) |
DCB DAUTHCTRL: Secure invasive debug enable select Mask
Definition at line 2073 of file core_cm35p.h.
| #define DCB_DSCSR_CDSKEY_Pos 17U |
DCB DSCSR: CDS write-enable key Position
Definition at line 2076 of file core_cm35p.h.
| #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) |
DCB DSCSR: CDS write-enable key Mask
Definition at line 2077 of file core_cm35p.h.
| #define DCB_DSCSR_CDS_Pos 16U |
DCB DSCSR: Current domain Secure Position
Definition at line 2079 of file core_cm35p.h.
| #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) |
DCB DSCSR: Current domain Secure Mask
Definition at line 2080 of file core_cm35p.h.
| #define DCB_DSCSR_SBRSEL_Pos 1U |
DCB DSCSR: Secure banked register select Position
Definition at line 2082 of file core_cm35p.h.
| #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) |
DCB DSCSR: Secure banked register select Mask
Definition at line 2083 of file core_cm35p.h.
| #define DCB_DSCSR_SBRSELEN_Pos 0U |
DCB DSCSR: Secure banked register select enable Position
Definition at line 2085 of file core_cm35p.h.
| #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) |
DCB DSCSR: Secure banked register select enable Mask
Definition at line 2086 of file core_cm35p.h.
| #define DIB_DLAR_KEY_Pos 0U |
DIB DLAR: KEY Position
Definition at line 2112 of file core_cm35p.h.
| #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) |
DIB DLAR: KEY Mask
Definition at line 2113 of file core_cm35p.h.
| #define DIB_DLSR_nTT_Pos 2U |
DIB DLSR: Not thirty-two bit Position
Definition at line 2116 of file core_cm35p.h.
| #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) |
DIB DLSR: Not thirty-two bit Mask
Definition at line 2117 of file core_cm35p.h.
| #define DIB_DLSR_SLK_Pos 1U |
DIB DLSR: Software Lock status Position
Definition at line 2119 of file core_cm35p.h.
| #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) |
DIB DLSR: Software Lock status Mask
Definition at line 2120 of file core_cm35p.h.
| #define DIB_DLSR_SLI_Pos 0U |
DIB DLSR: Software Lock implemented Position
Definition at line 2122 of file core_cm35p.h.
| #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) |
DIB DLSR: Software Lock implemented Mask
Definition at line 2123 of file core_cm35p.h.
| #define DIB_DAUTHSTATUS_SNID_Pos 6U |
DIB DAUTHSTATUS: Secure Non-invasive Debug Position
Definition at line 2126 of file core_cm35p.h.
| #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) |
DIB DAUTHSTATUS: Secure Non-invasive Debug Mask
Definition at line 2127 of file core_cm35p.h.
| #define DIB_DAUTHSTATUS_SID_Pos 4U |
DIB DAUTHSTATUS: Secure Invasive Debug Position
Definition at line 2129 of file core_cm35p.h.
| #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) |
DIB DAUTHSTATUS: Secure Invasive Debug Mask
Definition at line 2130 of file core_cm35p.h.
| #define DIB_DAUTHSTATUS_NSNID_Pos 2U |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position
Definition at line 2132 of file core_cm35p.h.
| #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask
Definition at line 2133 of file core_cm35p.h.
| #define DIB_DAUTHSTATUS_NSID_Pos 0U |
DIB DAUTHSTATUS: Non-secure Invasive Debug Position
Definition at line 2135 of file core_cm35p.h.
| #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) |
DIB DAUTHSTATUS: Non-secure Invasive Debug Mask
Definition at line 2136 of file core_cm35p.h.
| #define DIB_DDEVARCH_ARCHITECT_Pos 21U |
DIB DDEVARCH: Architect Position
Definition at line 2139 of file core_cm35p.h.
| #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) |
DIB DDEVARCH: Architect Mask
Definition at line 2140 of file core_cm35p.h.
| #define DIB_DDEVARCH_PRESENT_Pos 20U |
DIB DDEVARCH: DEVARCH Present Position
Definition at line 2142 of file core_cm35p.h.
| #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) |
DIB DDEVARCH: DEVARCH Present Mask
Definition at line 2143 of file core_cm35p.h.
| #define DIB_DDEVARCH_REVISION_Pos 16U |
DIB DDEVARCH: Revision Position
Definition at line 2145 of file core_cm35p.h.
| #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) |
DIB DDEVARCH: Revision Mask
Definition at line 2146 of file core_cm35p.h.
| #define DIB_DDEVARCH_ARCHVER_Pos 12U |
DIB DDEVARCH: Architecture Version Position
Definition at line 2148 of file core_cm35p.h.
| #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) |
DIB DDEVARCH: Architecture Version Mask
Definition at line 2149 of file core_cm35p.h.
| #define DIB_DDEVARCH_ARCHPART_Pos 0U |
DIB DDEVARCH: Architecture Part Position
Definition at line 2151 of file core_cm35p.h.
| #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) |
DIB DDEVARCH: Architecture Part Mask
Definition at line 2152 of file core_cm35p.h.
| #define DIB_DDEVTYPE_SUB_Pos 4U |
DIB DDEVTYPE: Sub-type Position
Definition at line 2155 of file core_cm35p.h.
| #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) |
DIB DDEVTYPE: Sub-type Mask
Definition at line 2156 of file core_cm35p.h.
| #define DIB_DDEVTYPE_MAJOR_Pos 0U |
DIB DDEVTYPE: Major type Position
Definition at line 2158 of file core_cm35p.h.
| #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) |
DIB DDEVTYPE: Major type Mask
Definition at line 2159 of file core_cm35p.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 2178 of file core_cm35p.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 2186 of file core_cm35p.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 2199 of file core_cm35p.h.
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
Definition at line 2200 of file core_cm35p.h.
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
Definition at line 2201 of file core_cm35p.h.
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
Definition at line 2202 of file core_cm35p.h.
| #define DCB_BASE (0xE000EDF0UL) |
DCB Base Address
Definition at line 2204 of file core_cm35p.h.
| #define DIB_BASE (0xE000EFB0UL) |
DIB Base Address
Definition at line 2205 of file core_cm35p.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 2206 of file core_cm35p.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 2207 of file core_cm35p.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 2208 of file core_cm35p.h.
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
Definition at line 2210 of file core_cm35p.h.
SCB configuration struct
Definition at line 2211 of file core_cm35p.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 2212 of file core_cm35p.h.
NVIC configuration struct
Definition at line 2213 of file core_cm35p.h.
ITM configuration struct
Definition at line 2214 of file core_cm35p.h.
DWT configuration struct
Definition at line 2215 of file core_cm35p.h.
TPI configuration struct
Definition at line 2216 of file core_cm35p.h.
DCB configuration struct
Definition at line 2218 of file core_cm35p.h.
DIB configuration struct
Definition at line 2219 of file core_cm35p.h.
| #define MPU_BASE (SCS_BASE + 0x0D90UL) |
Memory Protection Unit
Definition at line 2222 of file core_cm35p.h.
Memory Protection Unit
Definition at line 2223 of file core_cm35p.h.
| #define FPU_BASE (SCS_BASE + 0x0F30UL) |
Floating Point Unit
Definition at line 2231 of file core_cm35p.h.
Floating Point Unit
Definition at line 2232 of file core_cm35p.h.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 3201 of file core_cm35p.h.
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
Definition at line 429 of file core_cm4.h.
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
Definition at line 430 of file core_cm4.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 471 of file core_cm4.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 472 of file core_cm4.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 474 of file core_cm4.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 475 of file core_cm4.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 477 of file core_cm4.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 478 of file core_cm4.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 480 of file core_cm4.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 481 of file core_cm4.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 483 of file core_cm4.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 484 of file core_cm4.h.
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
Definition at line 487 of file core_cm4.h.
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
Definition at line 488 of file core_cm4.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 490 of file core_cm4.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 491 of file core_cm4.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 493 of file core_cm4.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 494 of file core_cm4.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 496 of file core_cm4.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 497 of file core_cm4.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 499 of file core_cm4.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 500 of file core_cm4.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 502 of file core_cm4.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 503 of file core_cm4.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 505 of file core_cm4.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 506 of file core_cm4.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 508 of file core_cm4.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 509 of file core_cm4.h.
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
Definition at line 511 of file core_cm4.h.
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
Definition at line 512 of file core_cm4.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 514 of file core_cm4.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 515 of file core_cm4.h.
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
Definition at line 518 of file core_cm4.h.
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
Definition at line 519 of file core_cm4.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 522 of file core_cm4.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 523 of file core_cm4.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 525 of file core_cm4.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 526 of file core_cm4.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 528 of file core_cm4.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 529 of file core_cm4.h.
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
Definition at line 531 of file core_cm4.h.
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
Definition at line 532 of file core_cm4.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 534 of file core_cm4.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 535 of file core_cm4.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 537 of file core_cm4.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 538 of file core_cm4.h.
| #define SCB_AIRCR_VECTRESET_Pos 0U |
SCB AIRCR: VECTRESET Position
Definition at line 540 of file core_cm4.h.
| #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) |
SCB AIRCR: VECTRESET Mask
Definition at line 541 of file core_cm4.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 544 of file core_cm4.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 545 of file core_cm4.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 547 of file core_cm4.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 548 of file core_cm4.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 550 of file core_cm4.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 551 of file core_cm4.h.
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
Definition at line 554 of file core_cm4.h.
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
Definition at line 555 of file core_cm4.h.
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
Definition at line 557 of file core_cm4.h.
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
Definition at line 558 of file core_cm4.h.
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
Definition at line 560 of file core_cm4.h.
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
Definition at line 561 of file core_cm4.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 563 of file core_cm4.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 564 of file core_cm4.h.
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
Definition at line 566 of file core_cm4.h.
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
Definition at line 567 of file core_cm4.h.
| #define SCB_CCR_NONBASETHRDENA_Pos 0U |
SCB CCR: NONBASETHRDENA Position
Definition at line 569 of file core_cm4.h.
| #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) |
SCB CCR: NONBASETHRDENA Mask
Definition at line 570 of file core_cm4.h.
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
Definition at line 573 of file core_cm4.h.
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
Definition at line 574 of file core_cm4.h.
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
Definition at line 576 of file core_cm4.h.
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
Definition at line 577 of file core_cm4.h.
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
Definition at line 579 of file core_cm4.h.
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
Definition at line 580 of file core_cm4.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 582 of file core_cm4.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 583 of file core_cm4.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
Definition at line 585 of file core_cm4.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
Definition at line 586 of file core_cm4.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
Definition at line 588 of file core_cm4.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
Definition at line 589 of file core_cm4.h.
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
Definition at line 591 of file core_cm4.h.
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
Definition at line 592 of file core_cm4.h.
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
Definition at line 594 of file core_cm4.h.
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
Definition at line 595 of file core_cm4.h.
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
Definition at line 597 of file core_cm4.h.
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
Definition at line 598 of file core_cm4.h.
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
Definition at line 600 of file core_cm4.h.
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
Definition at line 601 of file core_cm4.h.
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
Definition at line 603 of file core_cm4.h.
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
Definition at line 604 of file core_cm4.h.
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
Definition at line 606 of file core_cm4.h.
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
Definition at line 607 of file core_cm4.h.
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
Definition at line 609 of file core_cm4.h.
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
Definition at line 610 of file core_cm4.h.
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
Definition at line 612 of file core_cm4.h.
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
Definition at line 613 of file core_cm4.h.
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
Definition at line 616 of file core_cm4.h.
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
Definition at line 617 of file core_cm4.h.
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
Definition at line 619 of file core_cm4.h.
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
Definition at line 620 of file core_cm4.h.
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
Definition at line 622 of file core_cm4.h.
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
Definition at line 623 of file core_cm4.h.
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
Definition at line 626 of file core_cm4.h.
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
Definition at line 627 of file core_cm4.h.
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
Definition at line 629 of file core_cm4.h.
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
Definition at line 630 of file core_cm4.h.
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
Definition at line 632 of file core_cm4.h.
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
Definition at line 633 of file core_cm4.h.
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
Definition at line 635 of file core_cm4.h.
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
Definition at line 636 of file core_cm4.h.
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
Definition at line 638 of file core_cm4.h.
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
Definition at line 639 of file core_cm4.h.
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
Definition at line 641 of file core_cm4.h.
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
Definition at line 642 of file core_cm4.h.
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
Definition at line 645 of file core_cm4.h.
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
Definition at line 646 of file core_cm4.h.
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
Definition at line 648 of file core_cm4.h.
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
Definition at line 649 of file core_cm4.h.
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
Definition at line 651 of file core_cm4.h.
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
Definition at line 652 of file core_cm4.h.
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
Definition at line 654 of file core_cm4.h.
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
Definition at line 655 of file core_cm4.h.
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
Definition at line 657 of file core_cm4.h.
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
Definition at line 658 of file core_cm4.h.
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
Definition at line 660 of file core_cm4.h.
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
Definition at line 661 of file core_cm4.h.
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
Definition at line 663 of file core_cm4.h.
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
Definition at line 664 of file core_cm4.h.
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
Definition at line 667 of file core_cm4.h.
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
Definition at line 668 of file core_cm4.h.
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
Definition at line 670 of file core_cm4.h.
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
Definition at line 671 of file core_cm4.h.
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
Definition at line 673 of file core_cm4.h.
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
Definition at line 674 of file core_cm4.h.
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
Definition at line 676 of file core_cm4.h.
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
Definition at line 677 of file core_cm4.h.
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
Definition at line 679 of file core_cm4.h.
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
Definition at line 680 of file core_cm4.h.
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
Definition at line 682 of file core_cm4.h.
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
Definition at line 683 of file core_cm4.h.
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
Definition at line 686 of file core_cm4.h.
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
Definition at line 687 of file core_cm4.h.
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
Definition at line 689 of file core_cm4.h.
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
Definition at line 690 of file core_cm4.h.
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
Definition at line 692 of file core_cm4.h.
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
Definition at line 693 of file core_cm4.h.
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
Definition at line 696 of file core_cm4.h.
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
Definition at line 697 of file core_cm4.h.
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
Definition at line 699 of file core_cm4.h.
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
Definition at line 700 of file core_cm4.h.
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
Definition at line 702 of file core_cm4.h.
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
Definition at line 703 of file core_cm4.h.
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
Definition at line 705 of file core_cm4.h.
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
Definition at line 706 of file core_cm4.h.
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
Definition at line 708 of file core_cm4.h.
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
Definition at line 709 of file core_cm4.h.
| #define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
Definition at line 732 of file core_cm4.h.
| #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
Definition at line 733 of file core_cm4.h.
| #define SCnSCB_ACTLR_DISFOLD_Pos 2U |
ACTLR: DISFOLD Position
Definition at line 742 of file core_cm4.h.
| #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) |
ACTLR: DISFOLD Mask
Definition at line 743 of file core_cm4.h.
| #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U |
ACTLR: DISDEFWBUF Position
Definition at line 745 of file core_cm4.h.
| #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) |
ACTLR: DISDEFWBUF Mask
Definition at line 746 of file core_cm4.h.
| #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U |
ACTLR: DISMCYCINT Position
Definition at line 748 of file core_cm4.h.
| #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) |
ACTLR: DISMCYCINT Mask
Definition at line 749 of file core_cm4.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 773 of file core_cm4.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 774 of file core_cm4.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 776 of file core_cm4.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 777 of file core_cm4.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 779 of file core_cm4.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 780 of file core_cm4.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 782 of file core_cm4.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 783 of file core_cm4.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 786 of file core_cm4.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 787 of file core_cm4.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 790 of file core_cm4.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 791 of file core_cm4.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 794 of file core_cm4.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 795 of file core_cm4.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 797 of file core_cm4.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 798 of file core_cm4.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 800 of file core_cm4.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 801 of file core_cm4.h.
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
Definition at line 850 of file core_cm4.h.
| #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
Definition at line 851 of file core_cm4.h.
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
Definition at line 854 of file core_cm4.h.
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
Definition at line 855 of file core_cm4.h.
| #define ITM_TCR_TraceBusID_Pos 16U |
ITM TCR: ATBID Position
Definition at line 857 of file core_cm4.h.
| #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) |
ITM TCR: ATBID Mask
Definition at line 858 of file core_cm4.h.
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
Definition at line 860 of file core_cm4.h.
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
Definition at line 861 of file core_cm4.h.
| #define ITM_TCR_TSPrescale_Pos 8U |
ITM TCR: TSPrescale Position
Definition at line 863 of file core_cm4.h.
| #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) |
ITM TCR: TSPrescale Mask
Definition at line 864 of file core_cm4.h.
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
Definition at line 866 of file core_cm4.h.
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
Definition at line 867 of file core_cm4.h.
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
Definition at line 869 of file core_cm4.h.
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
Definition at line 870 of file core_cm4.h.
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
Definition at line 872 of file core_cm4.h.
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
Definition at line 873 of file core_cm4.h.
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
Definition at line 875 of file core_cm4.h.
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
Definition at line 876 of file core_cm4.h.
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
Definition at line 878 of file core_cm4.h.
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
Definition at line 879 of file core_cm4.h.
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
Definition at line 882 of file core_cm4.h.
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
Definition at line 883 of file core_cm4.h.
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
Definition at line 885 of file core_cm4.h.
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
Definition at line 886 of file core_cm4.h.
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
Definition at line 888 of file core_cm4.h.
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
Definition at line 889 of file core_cm4.h.
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
Definition at line 932 of file core_cm4.h.
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
Definition at line 933 of file core_cm4.h.
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
Definition at line 935 of file core_cm4.h.
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
Definition at line 936 of file core_cm4.h.
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
Definition at line 938 of file core_cm4.h.
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
Definition at line 939 of file core_cm4.h.
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
Definition at line 941 of file core_cm4.h.
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
Definition at line 942 of file core_cm4.h.
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
Definition at line 944 of file core_cm4.h.
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
Definition at line 945 of file core_cm4.h.
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
Definition at line 947 of file core_cm4.h.
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
Definition at line 948 of file core_cm4.h.
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
Definition at line 950 of file core_cm4.h.
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
Definition at line 951 of file core_cm4.h.
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
Definition at line 953 of file core_cm4.h.
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
Definition at line 954 of file core_cm4.h.
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
Definition at line 956 of file core_cm4.h.
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
Definition at line 957 of file core_cm4.h.
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
Definition at line 959 of file core_cm4.h.
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
Definition at line 960 of file core_cm4.h.
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
Definition at line 962 of file core_cm4.h.
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
Definition at line 963 of file core_cm4.h.
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
Definition at line 965 of file core_cm4.h.
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
Definition at line 966 of file core_cm4.h.
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
Definition at line 968 of file core_cm4.h.
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
Definition at line 969 of file core_cm4.h.
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
Definition at line 971 of file core_cm4.h.
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
Definition at line 972 of file core_cm4.h.
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
Definition at line 974 of file core_cm4.h.
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
Definition at line 975 of file core_cm4.h.
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
Definition at line 977 of file core_cm4.h.
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
Definition at line 978 of file core_cm4.h.
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
Definition at line 980 of file core_cm4.h.
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
Definition at line 981 of file core_cm4.h.
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
Definition at line 983 of file core_cm4.h.
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
Definition at line 984 of file core_cm4.h.
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
Definition at line 987 of file core_cm4.h.
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
Definition at line 988 of file core_cm4.h.
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
Definition at line 991 of file core_cm4.h.
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
Definition at line 992 of file core_cm4.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
Definition at line 995 of file core_cm4.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
Definition at line 996 of file core_cm4.h.
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
Definition at line 999 of file core_cm4.h.
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
Definition at line 1000 of file core_cm4.h.
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
Definition at line 1003 of file core_cm4.h.
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
Definition at line 1004 of file core_cm4.h.
| #define DWT_MASK_MASK_Pos 0U |
DWT MASK: MASK Position
Definition at line 1007 of file core_cm4.h.
| #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) |
DWT MASK: MASK Mask
Definition at line 1008 of file core_cm4.h.
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
Definition at line 1011 of file core_cm4.h.
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
Definition at line 1012 of file core_cm4.h.
| #define DWT_FUNCTION_DATAVADDR1_Pos 16U |
DWT FUNCTION: DATAVADDR1 Position
Definition at line 1014 of file core_cm4.h.
| #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) |
DWT FUNCTION: DATAVADDR1 Mask
Definition at line 1015 of file core_cm4.h.
| #define DWT_FUNCTION_DATAVADDR0_Pos 12U |
DWT FUNCTION: DATAVADDR0 Position
Definition at line 1017 of file core_cm4.h.
| #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) |
DWT FUNCTION: DATAVADDR0 Mask
Definition at line 1018 of file core_cm4.h.
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
Definition at line 1020 of file core_cm4.h.
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
Definition at line 1021 of file core_cm4.h.
| #define DWT_FUNCTION_LNK1ENA_Pos 9U |
DWT FUNCTION: LNK1ENA Position
Definition at line 1023 of file core_cm4.h.
| #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) |
DWT FUNCTION: LNK1ENA Mask
Definition at line 1024 of file core_cm4.h.
| #define DWT_FUNCTION_DATAVMATCH_Pos 8U |
DWT FUNCTION: DATAVMATCH Position
Definition at line 1026 of file core_cm4.h.
| #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) |
DWT FUNCTION: DATAVMATCH Mask
Definition at line 1027 of file core_cm4.h.
| #define DWT_FUNCTION_CYCMATCH_Pos 7U |
DWT FUNCTION: CYCMATCH Position
Definition at line 1029 of file core_cm4.h.
| #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) |
DWT FUNCTION: CYCMATCH Mask
Definition at line 1030 of file core_cm4.h.
| #define DWT_FUNCTION_EMITRANGE_Pos 5U |
DWT FUNCTION: EMITRANGE Position
Definition at line 1032 of file core_cm4.h.
| #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) |
DWT FUNCTION: EMITRANGE Mask
Definition at line 1033 of file core_cm4.h.
| #define DWT_FUNCTION_FUNCTION_Pos 0U |
DWT FUNCTION: FUNCTION Position
Definition at line 1035 of file core_cm4.h.
| #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) |
DWT FUNCTION: FUNCTION Mask
Definition at line 1036 of file core_cm4.h.
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
Definition at line 1080 of file core_cm4.h.
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
Definition at line 1081 of file core_cm4.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 1084 of file core_cm4.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 1085 of file core_cm4.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 1088 of file core_cm4.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 1089 of file core_cm4.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 1091 of file core_cm4.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 1092 of file core_cm4.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 1094 of file core_cm4.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 1095 of file core_cm4.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 1097 of file core_cm4.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 1098 of file core_cm4.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 1101 of file core_cm4.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 1102 of file core_cm4.h.
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
Definition at line 1104 of file core_cm4.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 1105 of file core_cm4.h.
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
Definition at line 1108 of file core_cm4.h.
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
Definition at line 1109 of file core_cm4.h.
| #define TPI_FIFO0_ITM_ATVALID_Pos 29U |
TPI FIFO0: ITM_ATVALID Position
Definition at line 1112 of file core_cm4.h.
| #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
Definition at line 1113 of file core_cm4.h.
| #define TPI_FIFO0_ITM_bytecount_Pos 27U |
TPI FIFO0: ITM_bytecount Position
Definition at line 1115 of file core_cm4.h.
| #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
Definition at line 1116 of file core_cm4.h.
| #define TPI_FIFO0_ETM_ATVALID_Pos 26U |
TPI FIFO0: ETM_ATVALID Position
Definition at line 1118 of file core_cm4.h.
| #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
Definition at line 1119 of file core_cm4.h.
| #define TPI_FIFO0_ETM_bytecount_Pos 24U |
TPI FIFO0: ETM_bytecount Position
Definition at line 1121 of file core_cm4.h.
| #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
Definition at line 1122 of file core_cm4.h.
| #define TPI_FIFO0_ETM2_Pos 16U |
TPI FIFO0: ETM2 Position
Definition at line 1124 of file core_cm4.h.
| #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
Definition at line 1125 of file core_cm4.h.
| #define TPI_FIFO0_ETM1_Pos 8U |
TPI FIFO0: ETM1 Position
Definition at line 1127 of file core_cm4.h.
| #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
Definition at line 1128 of file core_cm4.h.
| #define TPI_FIFO0_ETM0_Pos 0U |
TPI FIFO0: ETM0 Position
Definition at line 1130 of file core_cm4.h.
| #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
TPI FIFO0: ETM0 Mask
Definition at line 1131 of file core_cm4.h.
| #define TPI_ITATBCTR2_ATREADY2_Pos 0U |
TPI ITATBCTR2: ATREADY2 Position
Definition at line 1134 of file core_cm4.h.
| #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) |
TPI ITATBCTR2: ATREADY2 Mask
Definition at line 1135 of file core_cm4.h.
| #define TPI_ITATBCTR2_ATREADY1_Pos 0U |
TPI ITATBCTR2: ATREADY1 Position
Definition at line 1137 of file core_cm4.h.
| #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) |
TPI ITATBCTR2: ATREADY1 Mask
Definition at line 1138 of file core_cm4.h.
| #define TPI_FIFO1_ITM_ATVALID_Pos 29U |
TPI FIFO1: ITM_ATVALID Position
Definition at line 1141 of file core_cm4.h.
| #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
Definition at line 1142 of file core_cm4.h.
| #define TPI_FIFO1_ITM_bytecount_Pos 27U |
TPI FIFO1: ITM_bytecount Position
Definition at line 1144 of file core_cm4.h.
| #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
Definition at line 1145 of file core_cm4.h.
| #define TPI_FIFO1_ETM_ATVALID_Pos 26U |
TPI FIFO1: ETM_ATVALID Position
Definition at line 1147 of file core_cm4.h.
| #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
Definition at line 1148 of file core_cm4.h.
| #define TPI_FIFO1_ETM_bytecount_Pos 24U |
TPI FIFO1: ETM_bytecount Position
Definition at line 1150 of file core_cm4.h.
| #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
Definition at line 1151 of file core_cm4.h.
| #define TPI_FIFO1_ITM2_Pos 16U |
TPI FIFO1: ITM2 Position
Definition at line 1153 of file core_cm4.h.
| #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
Definition at line 1154 of file core_cm4.h.
| #define TPI_FIFO1_ITM1_Pos 8U |
TPI FIFO1: ITM1 Position
Definition at line 1156 of file core_cm4.h.
| #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
Definition at line 1157 of file core_cm4.h.
| #define TPI_FIFO1_ITM0_Pos 0U |
TPI FIFO1: ITM0 Position
Definition at line 1159 of file core_cm4.h.
| #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
TPI FIFO1: ITM0 Mask
Definition at line 1160 of file core_cm4.h.
| #define TPI_ITATBCTR0_ATREADY2_Pos 0U |
TPI ITATBCTR0: ATREADY2 Position
Definition at line 1163 of file core_cm4.h.
| #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) |
TPI ITATBCTR0: ATREADY2 Mask
Definition at line 1164 of file core_cm4.h.
| #define TPI_ITATBCTR0_ATREADY1_Pos 0U |
TPI ITATBCTR0: ATREADY1 Position
Definition at line 1166 of file core_cm4.h.
| #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) |
TPI ITATBCTR0: ATREADY1 Mask
Definition at line 1167 of file core_cm4.h.
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
Definition at line 1170 of file core_cm4.h.
| #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
Definition at line 1171 of file core_cm4.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 1174 of file core_cm4.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1175 of file core_cm4.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 1177 of file core_cm4.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1178 of file core_cm4.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 1180 of file core_cm4.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1181 of file core_cm4.h.
| #define TPI_DEVID_MinBufSz_Pos 6U |
TPI DEVID: MinBufSz Position
Definition at line 1183 of file core_cm4.h.
| #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
Definition at line 1184 of file core_cm4.h.
| #define TPI_DEVID_AsynClkIn_Pos 5U |
TPI DEVID: AsynClkIn Position
Definition at line 1186 of file core_cm4.h.
| #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
Definition at line 1187 of file core_cm4.h.
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
Definition at line 1189 of file core_cm4.h.
| #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
Definition at line 1190 of file core_cm4.h.
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
Definition at line 1193 of file core_cm4.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 1194 of file core_cm4.h.
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
Definition at line 1196 of file core_cm4.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1197 of file core_cm4.h.
| #define MPU_TYPE_IREGION_Pos 16U |
MPU TYPE: IREGION Position
Definition at line 1231 of file core_cm4.h.
| #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) |
MPU TYPE: IREGION Mask
Definition at line 1232 of file core_cm4.h.
| #define MPU_TYPE_DREGION_Pos 8U |
MPU TYPE: DREGION Position
Definition at line 1234 of file core_cm4.h.
| #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) |
MPU TYPE: DREGION Mask
Definition at line 1235 of file core_cm4.h.
| #define MPU_TYPE_SEPARATE_Pos 0U |
MPU TYPE: SEPARATE Position
Definition at line 1237 of file core_cm4.h.
| #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) |
MPU TYPE: SEPARATE Mask
Definition at line 1238 of file core_cm4.h.
| #define MPU_CTRL_PRIVDEFENA_Pos 2U |
MPU CTRL: PRIVDEFENA Position
Definition at line 1241 of file core_cm4.h.
| #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) |
MPU CTRL: PRIVDEFENA Mask
Definition at line 1242 of file core_cm4.h.
| #define MPU_CTRL_HFNMIENA_Pos 1U |
MPU CTRL: HFNMIENA Position
Definition at line 1244 of file core_cm4.h.
| #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) |
MPU CTRL: HFNMIENA Mask
Definition at line 1245 of file core_cm4.h.
| #define MPU_CTRL_ENABLE_Pos 0U |
MPU CTRL: ENABLE Position
Definition at line 1247 of file core_cm4.h.
| #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) |
MPU CTRL: ENABLE Mask
Definition at line 1248 of file core_cm4.h.
| #define MPU_RNR_REGION_Pos 0U |
MPU RNR: REGION Position
Definition at line 1251 of file core_cm4.h.
| #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) |
MPU RNR: REGION Mask
Definition at line 1252 of file core_cm4.h.
| #define MPU_RBAR_ADDR_Pos 5U |
MPU RBAR: ADDR Position
Definition at line 1255 of file core_cm4.h.
| #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) |
MPU RBAR: ADDR Mask
Definition at line 1256 of file core_cm4.h.
| #define MPU_RBAR_VALID_Pos 4U |
MPU RBAR: VALID Position
Definition at line 1258 of file core_cm4.h.
| #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) |
MPU RBAR: VALID Mask
Definition at line 1259 of file core_cm4.h.
| #define MPU_RBAR_REGION_Pos 0U |
MPU RBAR: REGION Position
Definition at line 1261 of file core_cm4.h.
| #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) |
MPU RBAR: REGION Mask
Definition at line 1262 of file core_cm4.h.
| #define MPU_RASR_ATTRS_Pos 16U |
MPU RASR: MPU Region Attribute field Position
Definition at line 1265 of file core_cm4.h.
| #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) |
MPU RASR: MPU Region Attribute field Mask
Definition at line 1266 of file core_cm4.h.
| #define MPU_RASR_XN_Pos 28U |
MPU RASR: ATTRS.XN Position
Definition at line 1268 of file core_cm4.h.
| #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) |
MPU RASR: ATTRS.XN Mask
Definition at line 1269 of file core_cm4.h.
| #define MPU_RASR_AP_Pos 24U |
MPU RASR: ATTRS.AP Position
Definition at line 1271 of file core_cm4.h.
| #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) |
MPU RASR: ATTRS.AP Mask
Definition at line 1272 of file core_cm4.h.
| #define MPU_RASR_TEX_Pos 19U |
MPU RASR: ATTRS.TEX Position
Definition at line 1274 of file core_cm4.h.
| #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) |
MPU RASR: ATTRS.TEX Mask
Definition at line 1275 of file core_cm4.h.
| #define MPU_RASR_S_Pos 18U |
MPU RASR: ATTRS.S Position
Definition at line 1277 of file core_cm4.h.
| #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) |
MPU RASR: ATTRS.S Mask
Definition at line 1278 of file core_cm4.h.
| #define MPU_RASR_C_Pos 17U |
MPU RASR: ATTRS.C Position
Definition at line 1280 of file core_cm4.h.
| #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) |
MPU RASR: ATTRS.C Mask
Definition at line 1281 of file core_cm4.h.
| #define MPU_RASR_B_Pos 16U |
MPU RASR: ATTRS.B Position
Definition at line 1283 of file core_cm4.h.
| #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) |
MPU RASR: ATTRS.B Mask
Definition at line 1284 of file core_cm4.h.
| #define MPU_RASR_SRD_Pos 8U |
MPU RASR: Sub-Region Disable Position
Definition at line 1286 of file core_cm4.h.
| #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) |
MPU RASR: Sub-Region Disable Mask
Definition at line 1287 of file core_cm4.h.
| #define MPU_RASR_SIZE_Pos 1U |
MPU RASR: Region Size Field Position
Definition at line 1289 of file core_cm4.h.
| #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) |
MPU RASR: Region Size Field Mask
Definition at line 1290 of file core_cm4.h.
| #define MPU_RASR_ENABLE_Pos 0U |
MPU RASR: Region enable bit Position
Definition at line 1292 of file core_cm4.h.
| #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) |
MPU RASR: Region enable bit Disable Mask
Definition at line 1293 of file core_cm4.h.
| #define FPU_FPCCR_ASPEN_Pos 31U |
FPCCR: ASPEN bit Position
Definition at line 1321 of file core_cm4.h.
| #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) |
FPCCR: ASPEN bit Mask
Definition at line 1322 of file core_cm4.h.
| #define FPU_FPCCR_LSPEN_Pos 30U |
FPCCR: LSPEN Position
Definition at line 1324 of file core_cm4.h.
| #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) |
FPCCR: LSPEN bit Mask
Definition at line 1325 of file core_cm4.h.
| #define FPU_FPCCR_MONRDY_Pos 8U |
FPCCR: MONRDY Position
Definition at line 1327 of file core_cm4.h.
| #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) |
FPCCR: MONRDY bit Mask
Definition at line 1328 of file core_cm4.h.
| #define FPU_FPCCR_BFRDY_Pos 6U |
FPCCR: BFRDY Position
Definition at line 1330 of file core_cm4.h.
| #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) |
FPCCR: BFRDY bit Mask
Definition at line 1331 of file core_cm4.h.
| #define FPU_FPCCR_MMRDY_Pos 5U |
FPCCR: MMRDY Position
Definition at line 1333 of file core_cm4.h.
| #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) |
FPCCR: MMRDY bit Mask
Definition at line 1334 of file core_cm4.h.
| #define FPU_FPCCR_HFRDY_Pos 4U |
FPCCR: HFRDY Position
Definition at line 1336 of file core_cm4.h.
| #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) |
FPCCR: HFRDY bit Mask
Definition at line 1337 of file core_cm4.h.
| #define FPU_FPCCR_THREAD_Pos 3U |
FPCCR: processor mode bit Position
Definition at line 1339 of file core_cm4.h.
| #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) |
FPCCR: processor mode active bit Mask
Definition at line 1340 of file core_cm4.h.
| #define FPU_FPCCR_USER_Pos 1U |
FPCCR: privilege level bit Position
Definition at line 1342 of file core_cm4.h.
| #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) |
FPCCR: privilege level bit Mask
Definition at line 1343 of file core_cm4.h.
| #define FPU_FPCCR_LSPACT_Pos 0U |
FPCCR: Lazy state preservation active bit Position
Definition at line 1345 of file core_cm4.h.
| #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) |
FPCCR: Lazy state preservation active bit Mask
Definition at line 1346 of file core_cm4.h.
| #define FPU_FPCAR_ADDRESS_Pos 3U |
FPCAR: ADDRESS bit Position
Definition at line 1349 of file core_cm4.h.
| #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) |
FPCAR: ADDRESS bit Mask
Definition at line 1350 of file core_cm4.h.
| #define FPU_FPDSCR_AHP_Pos 26U |
FPDSCR: AHP bit Position
Definition at line 1353 of file core_cm4.h.
| #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) |
FPDSCR: AHP bit Mask
Definition at line 1354 of file core_cm4.h.
| #define FPU_FPDSCR_DN_Pos 25U |
FPDSCR: DN bit Position
Definition at line 1356 of file core_cm4.h.
| #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) |
FPDSCR: DN bit Mask
Definition at line 1357 of file core_cm4.h.
| #define FPU_FPDSCR_FZ_Pos 24U |
FPDSCR: FZ bit Position
Definition at line 1359 of file core_cm4.h.
| #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) |
FPDSCR: FZ bit Mask
Definition at line 1360 of file core_cm4.h.
| #define FPU_FPDSCR_RMode_Pos 22U |
FPDSCR: RMode bit Position
Definition at line 1362 of file core_cm4.h.
| #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) |
FPDSCR: RMode bit Mask
Definition at line 1363 of file core_cm4.h.
| #define FPU_MVFR0_FP_rounding_modes_Pos 28U |
MVFR0: FP rounding modes bits Position
Definition at line 1366 of file core_cm4.h.
| #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) |
MVFR0: FP rounding modes bits Mask
Definition at line 1367 of file core_cm4.h.
| #define FPU_MVFR0_Short_vectors_Pos 24U |
MVFR0: Short vectors bits Position
Definition at line 1369 of file core_cm4.h.
| #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) |
MVFR0: Short vectors bits Mask
Definition at line 1370 of file core_cm4.h.
| #define FPU_MVFR0_Square_root_Pos 20U |
MVFR0: Square root bits Position
Definition at line 1372 of file core_cm4.h.
| #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) |
MVFR0: Square root bits Mask
Definition at line 1373 of file core_cm4.h.
| #define FPU_MVFR0_Divide_Pos 16U |
MVFR0: Divide bits Position
Definition at line 1375 of file core_cm4.h.
| #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) |
MVFR0: Divide bits Mask
Definition at line 1376 of file core_cm4.h.
| #define FPU_MVFR0_FP_excep_trapping_Pos 12U |
MVFR0: FP exception trapping bits Position
Definition at line 1378 of file core_cm4.h.
| #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) |
MVFR0: FP exception trapping bits Mask
Definition at line 1379 of file core_cm4.h.
| #define FPU_MVFR0_Double_precision_Pos 8U |
MVFR0: Double-precision bits Position
Definition at line 1381 of file core_cm4.h.
| #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) |
MVFR0: Double-precision bits Mask
Definition at line 1382 of file core_cm4.h.
| #define FPU_MVFR0_Single_precision_Pos 4U |
MVFR0: Single-precision bits Position
Definition at line 1384 of file core_cm4.h.
| #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) |
MVFR0: Single-precision bits Mask
Definition at line 1385 of file core_cm4.h.
| #define FPU_MVFR0_A_SIMD_registers_Pos 0U |
MVFR0: A_SIMD registers bits Position
Definition at line 1387 of file core_cm4.h.
| #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) |
MVFR0: A_SIMD registers bits Mask
Definition at line 1388 of file core_cm4.h.
| #define FPU_MVFR1_FP_fused_MAC_Pos 28U |
MVFR1: FP fused MAC bits Position
Definition at line 1391 of file core_cm4.h.
| #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) |
MVFR1: FP fused MAC bits Mask
Definition at line 1392 of file core_cm4.h.
| #define FPU_MVFR1_FP_HPFP_Pos 24U |
MVFR1: FP HPFP bits Position
Definition at line 1394 of file core_cm4.h.
| #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) |
MVFR1: FP HPFP bits Mask
Definition at line 1395 of file core_cm4.h.
| #define FPU_MVFR1_D_NaN_mode_Pos 4U |
MVFR1: D_NaN mode bits Position
Definition at line 1397 of file core_cm4.h.
| #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) |
MVFR1: D_NaN mode bits Mask
Definition at line 1398 of file core_cm4.h.
| #define FPU_MVFR1_FtZ_mode_Pos 0U |
MVFR1: FtZ mode bits Position
Definition at line 1400 of file core_cm4.h.
| #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) |
MVFR1: FtZ mode bits Mask
Definition at line 1401 of file core_cm4.h.
| #define CoreDebug_DHCSR_DBGKEY_Pos 16U |
CoreDebug DHCSR: DBGKEY Position
Definition at line 1430 of file core_cm4.h.
| #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
CoreDebug DHCSR: DBGKEY Mask
Definition at line 1431 of file core_cm4.h.
| #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
CoreDebug DHCSR: S_RESET_ST Position
Definition at line 1433 of file core_cm4.h.
| #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
CoreDebug DHCSR: S_RESET_ST Mask
Definition at line 1434 of file core_cm4.h.
| #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
CoreDebug DHCSR: S_RETIRE_ST Position
Definition at line 1436 of file core_cm4.h.
| #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
CoreDebug DHCSR: S_RETIRE_ST Mask
Definition at line 1437 of file core_cm4.h.
| #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
CoreDebug DHCSR: S_LOCKUP Position
Definition at line 1439 of file core_cm4.h.
| #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
CoreDebug DHCSR: S_LOCKUP Mask
Definition at line 1440 of file core_cm4.h.
| #define CoreDebug_DHCSR_S_SLEEP_Pos 18U |
CoreDebug DHCSR: S_SLEEP Position
Definition at line 1442 of file core_cm4.h.
| #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
CoreDebug DHCSR: S_SLEEP Mask
Definition at line 1443 of file core_cm4.h.
| #define CoreDebug_DHCSR_S_HALT_Pos 17U |
CoreDebug DHCSR: S_HALT Position
Definition at line 1445 of file core_cm4.h.
| #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
CoreDebug DHCSR: S_HALT Mask
Definition at line 1446 of file core_cm4.h.
| #define CoreDebug_DHCSR_S_REGRDY_Pos 16U |
CoreDebug DHCSR: S_REGRDY Position
Definition at line 1448 of file core_cm4.h.
| #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
CoreDebug DHCSR: S_REGRDY Mask
Definition at line 1449 of file core_cm4.h.
| #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U |
CoreDebug DHCSR: C_SNAPSTALL Position
Definition at line 1451 of file core_cm4.h.
| #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) |
CoreDebug DHCSR: C_SNAPSTALL Mask
Definition at line 1452 of file core_cm4.h.
| #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
CoreDebug DHCSR: C_MASKINTS Position
Definition at line 1454 of file core_cm4.h.
| #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
CoreDebug DHCSR: C_MASKINTS Mask
Definition at line 1455 of file core_cm4.h.
| #define CoreDebug_DHCSR_C_STEP_Pos 2U |
CoreDebug DHCSR: C_STEP Position
Definition at line 1457 of file core_cm4.h.
| #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
CoreDebug DHCSR: C_STEP Mask
Definition at line 1458 of file core_cm4.h.
| #define CoreDebug_DHCSR_C_HALT_Pos 1U |
CoreDebug DHCSR: C_HALT Position
Definition at line 1460 of file core_cm4.h.
| #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
CoreDebug DHCSR: C_HALT Mask
Definition at line 1461 of file core_cm4.h.
| #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
CoreDebug DHCSR: C_DEBUGEN Position
Definition at line 1463 of file core_cm4.h.
| #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
CoreDebug DHCSR: C_DEBUGEN Mask
Definition at line 1464 of file core_cm4.h.
| #define CoreDebug_DCRSR_REGWnR_Pos 16U |
CoreDebug DCRSR: REGWnR Position
Definition at line 1467 of file core_cm4.h.
| #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
CoreDebug DCRSR: REGWnR Mask
Definition at line 1468 of file core_cm4.h.
| #define CoreDebug_DCRSR_REGSEL_Pos 0U |
CoreDebug DCRSR: REGSEL Position
Definition at line 1470 of file core_cm4.h.
| #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
CoreDebug DCRSR: REGSEL Mask
Definition at line 1471 of file core_cm4.h.
| #define CoreDebug_DEMCR_TRCENA_Pos 24U |
CoreDebug DEMCR: TRCENA Position
Definition at line 1474 of file core_cm4.h.
| #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) |
CoreDebug DEMCR: TRCENA Mask
Definition at line 1475 of file core_cm4.h.
| #define CoreDebug_DEMCR_MON_REQ_Pos 19U |
CoreDebug DEMCR: MON_REQ Position
Definition at line 1477 of file core_cm4.h.
| #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) |
CoreDebug DEMCR: MON_REQ Mask
Definition at line 1478 of file core_cm4.h.
| #define CoreDebug_DEMCR_MON_STEP_Pos 18U |
CoreDebug DEMCR: MON_STEP Position
Definition at line 1480 of file core_cm4.h.
| #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) |
CoreDebug DEMCR: MON_STEP Mask
Definition at line 1481 of file core_cm4.h.
| #define CoreDebug_DEMCR_MON_PEND_Pos 17U |
CoreDebug DEMCR: MON_PEND Position
Definition at line 1483 of file core_cm4.h.
| #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) |
CoreDebug DEMCR: MON_PEND Mask
Definition at line 1484 of file core_cm4.h.
| #define CoreDebug_DEMCR_MON_EN_Pos 16U |
CoreDebug DEMCR: MON_EN Position
Definition at line 1486 of file core_cm4.h.
| #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) |
CoreDebug DEMCR: MON_EN Mask
Definition at line 1487 of file core_cm4.h.
| #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
CoreDebug DEMCR: VC_HARDERR Position
Definition at line 1489 of file core_cm4.h.
| #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
CoreDebug DEMCR: VC_HARDERR Mask
Definition at line 1490 of file core_cm4.h.
| #define CoreDebug_DEMCR_VC_INTERR_Pos 9U |
CoreDebug DEMCR: VC_INTERR Position
Definition at line 1492 of file core_cm4.h.
| #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) |
CoreDebug DEMCR: VC_INTERR Mask
Definition at line 1493 of file core_cm4.h.
| #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U |
CoreDebug DEMCR: VC_BUSERR Position
Definition at line 1495 of file core_cm4.h.
| #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) |
CoreDebug DEMCR: VC_BUSERR Mask
Definition at line 1496 of file core_cm4.h.
| #define CoreDebug_DEMCR_VC_STATERR_Pos 7U |
CoreDebug DEMCR: VC_STATERR Position
Definition at line 1498 of file core_cm4.h.
| #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) |
CoreDebug DEMCR: VC_STATERR Mask
Definition at line 1499 of file core_cm4.h.
| #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U |
CoreDebug DEMCR: VC_CHKERR Position
Definition at line 1501 of file core_cm4.h.
| #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) |
CoreDebug DEMCR: VC_CHKERR Mask
Definition at line 1502 of file core_cm4.h.
| #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U |
CoreDebug DEMCR: VC_NOCPERR Position
Definition at line 1504 of file core_cm4.h.
| #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) |
CoreDebug DEMCR: VC_NOCPERR Mask
Definition at line 1505 of file core_cm4.h.
| #define CoreDebug_DEMCR_VC_MMERR_Pos 4U |
CoreDebug DEMCR: VC_MMERR Position
Definition at line 1507 of file core_cm4.h.
| #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) |
CoreDebug DEMCR: VC_MMERR Mask
Definition at line 1508 of file core_cm4.h.
| #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
CoreDebug DEMCR: VC_CORERESET Position
Definition at line 1510 of file core_cm4.h.
| #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
CoreDebug DEMCR: VC_CORERESET Mask
Definition at line 1511 of file core_cm4.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 1529 of file core_cm4.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 1537 of file core_cm4.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 1550 of file core_cm4.h.
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
Definition at line 1551 of file core_cm4.h.
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
Definition at line 1552 of file core_cm4.h.
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
Definition at line 1553 of file core_cm4.h.
| #define CoreDebug_BASE (0xE000EDF0UL) |
Core Debug Base Address
Definition at line 1554 of file core_cm4.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 1555 of file core_cm4.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 1556 of file core_cm4.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 1557 of file core_cm4.h.
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
Definition at line 1559 of file core_cm4.h.
SCB configuration struct
Definition at line 1560 of file core_cm4.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 1561 of file core_cm4.h.
NVIC configuration struct
Definition at line 1562 of file core_cm4.h.
ITM configuration struct
Definition at line 1563 of file core_cm4.h.
DWT configuration struct
Definition at line 1564 of file core_cm4.h.
TPI configuration struct
Definition at line 1565 of file core_cm4.h.
| #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) |
Core Debug configuration struct
Definition at line 1566 of file core_cm4.h.
| #define MPU_BASE (SCS_BASE + 0x0D90UL) |
Memory Protection Unit
Definition at line 1569 of file core_cm4.h.
Memory Protection Unit
Definition at line 1570 of file core_cm4.h.
| #define FPU_BASE (SCS_BASE + 0x0F30UL) |
Floating Point Unit
Definition at line 1573 of file core_cm4.h.
Floating Point Unit
Definition at line 1574 of file core_cm4.h.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 2053 of file core_cm4.h.
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
Definition at line 497 of file core_cm55.h.
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
Definition at line 498 of file core_cm55.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 565 of file core_cm55.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 566 of file core_cm55.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 568 of file core_cm55.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 569 of file core_cm55.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 571 of file core_cm55.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 572 of file core_cm55.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 574 of file core_cm55.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 575 of file core_cm55.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 577 of file core_cm55.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 578 of file core_cm55.h.
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
Definition at line 581 of file core_cm55.h.
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
Definition at line 582 of file core_cm55.h.
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
Definition at line 584 of file core_cm55.h.
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
Definition at line 585 of file core_cm55.h.
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
Definition at line 587 of file core_cm55.h.
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
Definition at line 588 of file core_cm55.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 590 of file core_cm55.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 591 of file core_cm55.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 593 of file core_cm55.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 594 of file core_cm55.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 596 of file core_cm55.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 597 of file core_cm55.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 599 of file core_cm55.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 600 of file core_cm55.h.
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
Definition at line 602 of file core_cm55.h.
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
Definition at line 603 of file core_cm55.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 605 of file core_cm55.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 606 of file core_cm55.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 608 of file core_cm55.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 609 of file core_cm55.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 611 of file core_cm55.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 612 of file core_cm55.h.
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
Definition at line 614 of file core_cm55.h.
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
Definition at line 615 of file core_cm55.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 617 of file core_cm55.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 618 of file core_cm55.h.
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
Definition at line 621 of file core_cm55.h.
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
Definition at line 622 of file core_cm55.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 625 of file core_cm55.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 626 of file core_cm55.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 628 of file core_cm55.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 629 of file core_cm55.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 631 of file core_cm55.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 632 of file core_cm55.h.
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
Definition at line 634 of file core_cm55.h.
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
Definition at line 635 of file core_cm55.h.
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
Definition at line 637 of file core_cm55.h.
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
Definition at line 638 of file core_cm55.h.
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
Definition at line 640 of file core_cm55.h.
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
Definition at line 641 of file core_cm55.h.
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
Definition at line 649 of file core_cm55.h.
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
Definition at line 650 of file core_cm55.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 652 of file core_cm55.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 653 of file core_cm55.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 655 of file core_cm55.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 656 of file core_cm55.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 659 of file core_cm55.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 660 of file core_cm55.h.
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
Definition at line 662 of file core_cm55.h.
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
Definition at line 663 of file core_cm55.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 665 of file core_cm55.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 666 of file core_cm55.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 668 of file core_cm55.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 669 of file core_cm55.h.
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
SCB CCR: Branch prediction enable bit Position
Definition at line 678 of file core_cm55.h.
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
SCB CCR: Branch prediction enable bit Mask
Definition at line 679 of file core_cm55.h.
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
SCB CCR: Instruction cache enable bit Position
Definition at line 681 of file core_cm55.h.
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
SCB CCR: Instruction cache enable bit Mask
Definition at line 682 of file core_cm55.h.
| #define SCB_CCR_DC_Pos 16U |
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
Definition at line 687 of file core_cm55.h.
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
Definition at line 688 of file core_cm55.h.
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
Definition at line 690 of file core_cm55.h.
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
Definition at line 691 of file core_cm55.h.
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
Definition at line 693 of file core_cm55.h.
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
Definition at line 694 of file core_cm55.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 696 of file core_cm55.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 697 of file core_cm55.h.
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
Definition at line 699 of file core_cm55.h.
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
Definition at line 700 of file core_cm55.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
Definition at line 703 of file core_cm55.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
Definition at line 704 of file core_cm55.h.
| #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
SCB SHCSR: SECUREFAULTPENDED Position
Definition at line 706 of file core_cm55.h.
| #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
SCB SHCSR: SECUREFAULTPENDED Mask
Definition at line 707 of file core_cm55.h.
| #define SCB_SHCSR_SECUREFAULTENA_Pos 19U |
SCB SHCSR: SECUREFAULTENA Position
Definition at line 709 of file core_cm55.h.
| #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
SCB SHCSR: SECUREFAULTENA Mask
Definition at line 710 of file core_cm55.h.
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
Definition at line 712 of file core_cm55.h.
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
Definition at line 713 of file core_cm55.h.
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
Definition at line 715 of file core_cm55.h.
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
Definition at line 716 of file core_cm55.h.
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
Definition at line 718 of file core_cm55.h.
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
Definition at line 719 of file core_cm55.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 721 of file core_cm55.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 722 of file core_cm55.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
Definition at line 724 of file core_cm55.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
Definition at line 725 of file core_cm55.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
Definition at line 727 of file core_cm55.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
Definition at line 728 of file core_cm55.h.
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
Definition at line 730 of file core_cm55.h.
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
Definition at line 731 of file core_cm55.h.
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
Definition at line 733 of file core_cm55.h.
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
Definition at line 734 of file core_cm55.h.
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
Definition at line 736 of file core_cm55.h.
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
Definition at line 737 of file core_cm55.h.
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
Definition at line 739 of file core_cm55.h.
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
Definition at line 740 of file core_cm55.h.
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
Definition at line 742 of file core_cm55.h.
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
Definition at line 743 of file core_cm55.h.
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
Definition at line 745 of file core_cm55.h.
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
Definition at line 746 of file core_cm55.h.
| #define SCB_SHCSR_SECUREFAULTACT_Pos 4U |
SCB SHCSR: SECUREFAULTACT Position
Definition at line 748 of file core_cm55.h.
| #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
SCB SHCSR: SECUREFAULTACT Mask
Definition at line 749 of file core_cm55.h.
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
Definition at line 751 of file core_cm55.h.
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
Definition at line 752 of file core_cm55.h.
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
Definition at line 754 of file core_cm55.h.
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
Definition at line 755 of file core_cm55.h.
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
Definition at line 757 of file core_cm55.h.
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
Definition at line 758 of file core_cm55.h.
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
Definition at line 760 of file core_cm55.h.
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
Definition at line 761 of file core_cm55.h.
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
Definition at line 764 of file core_cm55.h.
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
Definition at line 765 of file core_cm55.h.
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
Definition at line 767 of file core_cm55.h.
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
Definition at line 768 of file core_cm55.h.
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
Definition at line 770 of file core_cm55.h.
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
Definition at line 771 of file core_cm55.h.
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
Definition at line 774 of file core_cm55.h.
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
Definition at line 775 of file core_cm55.h.
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
Definition at line 777 of file core_cm55.h.
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
Definition at line 778 of file core_cm55.h.
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
Definition at line 780 of file core_cm55.h.
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
Definition at line 781 of file core_cm55.h.
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
Definition at line 783 of file core_cm55.h.
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
Definition at line 784 of file core_cm55.h.
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
Definition at line 786 of file core_cm55.h.
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
Definition at line 787 of file core_cm55.h.
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
Definition at line 789 of file core_cm55.h.
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
Definition at line 790 of file core_cm55.h.
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
Definition at line 793 of file core_cm55.h.
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
Definition at line 794 of file core_cm55.h.
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
Definition at line 796 of file core_cm55.h.
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
Definition at line 797 of file core_cm55.h.
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
Definition at line 799 of file core_cm55.h.
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
Definition at line 800 of file core_cm55.h.
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
Definition at line 802 of file core_cm55.h.
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
Definition at line 803 of file core_cm55.h.
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
Definition at line 805 of file core_cm55.h.
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
Definition at line 806 of file core_cm55.h.
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
Definition at line 808 of file core_cm55.h.
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
Definition at line 809 of file core_cm55.h.
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
Definition at line 811 of file core_cm55.h.
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
Definition at line 812 of file core_cm55.h.
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
Definition at line 815 of file core_cm55.h.
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
Definition at line 816 of file core_cm55.h.
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
Definition at line 818 of file core_cm55.h.
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
Definition at line 819 of file core_cm55.h.
| #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
SCB CFSR (UFSR): STKOF Position
Definition at line 821 of file core_cm55.h.
| #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
SCB CFSR (UFSR): STKOF Mask
Definition at line 822 of file core_cm55.h.
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
Definition at line 824 of file core_cm55.h.
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
Definition at line 825 of file core_cm55.h.
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
Definition at line 827 of file core_cm55.h.
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
Definition at line 828 of file core_cm55.h.
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
Definition at line 830 of file core_cm55.h.
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
Definition at line 831 of file core_cm55.h.
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
Definition at line 833 of file core_cm55.h.
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
Definition at line 834 of file core_cm55.h.
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
Definition at line 837 of file core_cm55.h.
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
Definition at line 838 of file core_cm55.h.
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
Definition at line 840 of file core_cm55.h.
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
Definition at line 841 of file core_cm55.h.
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
Definition at line 843 of file core_cm55.h.
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
Definition at line 844 of file core_cm55.h.
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
Definition at line 850 of file core_cm55.h.
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
Definition at line 851 of file core_cm55.h.
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
Definition at line 853 of file core_cm55.h.
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
Definition at line 854 of file core_cm55.h.
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
Definition at line 856 of file core_cm55.h.
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
Definition at line 857 of file core_cm55.h.
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
Definition at line 859 of file core_cm55.h.
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
Definition at line 860 of file core_cm55.h.
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
Definition at line 862 of file core_cm55.h.
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
Definition at line 863 of file core_cm55.h.
| #define SCB_NSACR_CP11_Pos 11U |
SCB NSACR: CP11 Position
Definition at line 866 of file core_cm55.h.
| #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
SCB NSACR: CP11 Mask
Definition at line 867 of file core_cm55.h.
| #define SCB_NSACR_CP10_Pos 10U |
SCB NSACR: CP10 Position
Definition at line 869 of file core_cm55.h.
| #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
SCB NSACR: CP10 Mask
Definition at line 870 of file core_cm55.h.
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
Definition at line 904 of file core_cm55.h.
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
Definition at line 905 of file core_cm55.h.
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
Definition at line 907 of file core_cm55.h.
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
Definition at line 908 of file core_cm55.h.
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
Definition at line 911 of file core_cm55.h.
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
Definition at line 912 of file core_cm55.h.
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
Definition at line 914 of file core_cm55.h.
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
Definition at line 915 of file core_cm55.h.
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
Definition at line 917 of file core_cm55.h.
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
Definition at line 918 of file core_cm55.h.
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
Definition at line 920 of file core_cm55.h.
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
Definition at line 921 of file core_cm55.h.
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
Definition at line 923 of file core_cm55.h.
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
Definition at line 924 of file core_cm55.h.
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
Definition at line 927 of file core_cm55.h.
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
Definition at line 928 of file core_cm55.h.
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
Definition at line 930 of file core_cm55.h.
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
Definition at line 931 of file core_cm55.h.
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
Definition at line 933 of file core_cm55.h.
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
Definition at line 934 of file core_cm55.h.
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
Definition at line 936 of file core_cm55.h.
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
Definition at line 937 of file core_cm55.h.
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
Definition at line 939 of file core_cm55.h.
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
Definition at line 940 of file core_cm55.h.
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
Definition at line 942 of file core_cm55.h.
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
Definition at line 943 of file core_cm55.h.
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
Definition at line 945 of file core_cm55.h.
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
Definition at line 946 of file core_cm55.h.
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
Definition at line 949 of file core_cm55.h.
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
Definition at line 950 of file core_cm55.h.
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
Definition at line 952 of file core_cm55.h.
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
Definition at line 953 of file core_cm55.h.
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
Definition at line 956 of file core_cm55.h.
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
Definition at line 957 of file core_cm55.h.
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
Definition at line 970 of file core_cm55.h.
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
Definition at line 971 of file core_cm55.h.
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
Definition at line 973 of file core_cm55.h.
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
Definition at line 974 of file core_cm55.h.
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
Definition at line 977 of file core_cm55.h.
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
Definition at line 978 of file core_cm55.h.
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
Definition at line 980 of file core_cm55.h.
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
Definition at line 981 of file core_cm55.h.
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
Definition at line 984 of file core_cm55.h.
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
Definition at line 985 of file core_cm55.h.
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
Definition at line 987 of file core_cm55.h.
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
Definition at line 988 of file core_cm55.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 1080 of file core_cm55.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 1081 of file core_cm55.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 1083 of file core_cm55.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 1084 of file core_cm55.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 1086 of file core_cm55.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 1087 of file core_cm55.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 1089 of file core_cm55.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 1090 of file core_cm55.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 1093 of file core_cm55.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 1094 of file core_cm55.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 1097 of file core_cm55.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 1098 of file core_cm55.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 1101 of file core_cm55.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 1102 of file core_cm55.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 1104 of file core_cm55.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 1105 of file core_cm55.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 1107 of file core_cm55.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 1108 of file core_cm55.h.
| #define ITM_STIM_DISABLED_Pos 1U |
ITM STIM: DISABLED Position
Definition at line 1160 of file core_cm55.h.
| #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) |
ITM STIM: DISABLED Mask
Definition at line 1161 of file core_cm55.h.
| #define ITM_STIM_FIFOREADY_Pos 0U |
ITM STIM: FIFOREADY Position
Definition at line 1163 of file core_cm55.h.
| #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) |
ITM STIM: FIFOREADY Mask
Definition at line 1164 of file core_cm55.h.
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
Definition at line 1167 of file core_cm55.h.
| #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
Definition at line 1168 of file core_cm55.h.
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
Definition at line 1171 of file core_cm55.h.
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
Definition at line 1172 of file core_cm55.h.
| #define ITM_TCR_TRACEBUSID_Pos 16U |
ITM TCR: ATBID Position
Definition at line 1174 of file core_cm55.h.
| #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) |
ITM TCR: ATBID Mask
Definition at line 1175 of file core_cm55.h.
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
Definition at line 1177 of file core_cm55.h.
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
Definition at line 1178 of file core_cm55.h.
| #define ITM_TCR_TSPRESCALE_Pos 8U |
ITM TCR: TSPRESCALE Position
Definition at line 1180 of file core_cm55.h.
| #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) |
ITM TCR: TSPRESCALE Mask
Definition at line 1181 of file core_cm55.h.
| #define ITM_TCR_STALLENA_Pos 5U |
ITM TCR: STALLENA Position
Definition at line 1183 of file core_cm55.h.
| #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) |
ITM TCR: STALLENA Mask
Definition at line 1184 of file core_cm55.h.
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
Definition at line 1186 of file core_cm55.h.
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
Definition at line 1187 of file core_cm55.h.
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
Definition at line 1189 of file core_cm55.h.
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
Definition at line 1190 of file core_cm55.h.
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
Definition at line 1192 of file core_cm55.h.
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
Definition at line 1193 of file core_cm55.h.
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
Definition at line 1195 of file core_cm55.h.
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
Definition at line 1196 of file core_cm55.h.
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
Definition at line 1198 of file core_cm55.h.
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
Definition at line 1199 of file core_cm55.h.
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
Definition at line 1202 of file core_cm55.h.
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
Definition at line 1203 of file core_cm55.h.
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
Definition at line 1205 of file core_cm55.h.
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
Definition at line 1206 of file core_cm55.h.
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
Definition at line 1208 of file core_cm55.h.
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
Definition at line 1209 of file core_cm55.h.
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
Definition at line 1304 of file core_cm55.h.
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
Definition at line 1305 of file core_cm55.h.
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
Definition at line 1307 of file core_cm55.h.
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
Definition at line 1308 of file core_cm55.h.
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
Definition at line 1310 of file core_cm55.h.
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
Definition at line 1311 of file core_cm55.h.
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
Definition at line 1313 of file core_cm55.h.
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
Definition at line 1314 of file core_cm55.h.
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
Definition at line 1316 of file core_cm55.h.
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
Definition at line 1317 of file core_cm55.h.
| #define DWT_CTRL_CYCDISS_Pos 23U |
DWT CTRL: CYCDISS Position
Definition at line 1319 of file core_cm55.h.
| #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) |
DWT CTRL: CYCDISS Mask
Definition at line 1320 of file core_cm55.h.
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
Definition at line 1322 of file core_cm55.h.
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
Definition at line 1323 of file core_cm55.h.
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
Definition at line 1325 of file core_cm55.h.
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
Definition at line 1326 of file core_cm55.h.
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
Definition at line 1328 of file core_cm55.h.
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
Definition at line 1329 of file core_cm55.h.
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
Definition at line 1331 of file core_cm55.h.
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
Definition at line 1332 of file core_cm55.h.
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
Definition at line 1334 of file core_cm55.h.
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
Definition at line 1335 of file core_cm55.h.
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
Definition at line 1337 of file core_cm55.h.
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
Definition at line 1338 of file core_cm55.h.
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
Definition at line 1340 of file core_cm55.h.
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
Definition at line 1341 of file core_cm55.h.
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
Definition at line 1343 of file core_cm55.h.
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
Definition at line 1344 of file core_cm55.h.
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
Definition at line 1346 of file core_cm55.h.
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
Definition at line 1347 of file core_cm55.h.
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
Definition at line 1349 of file core_cm55.h.
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
Definition at line 1350 of file core_cm55.h.
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
Definition at line 1352 of file core_cm55.h.
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
Definition at line 1353 of file core_cm55.h.
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
Definition at line 1355 of file core_cm55.h.
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
Definition at line 1356 of file core_cm55.h.
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
Definition at line 1358 of file core_cm55.h.
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
Definition at line 1359 of file core_cm55.h.
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
Definition at line 1362 of file core_cm55.h.
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
Definition at line 1363 of file core_cm55.h.
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
Definition at line 1366 of file core_cm55.h.
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
Definition at line 1367 of file core_cm55.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
Definition at line 1370 of file core_cm55.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
Definition at line 1371 of file core_cm55.h.
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
Definition at line 1374 of file core_cm55.h.
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
Definition at line 1375 of file core_cm55.h.
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
Definition at line 1378 of file core_cm55.h.
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
Definition at line 1379 of file core_cm55.h.
| #define DWT_FUNCTION_ID_Pos 27U |
DWT FUNCTION: ID Position
Definition at line 1382 of file core_cm55.h.
| #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) |
DWT FUNCTION: ID Mask
Definition at line 1383 of file core_cm55.h.
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
Definition at line 1385 of file core_cm55.h.
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
Definition at line 1386 of file core_cm55.h.
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
Definition at line 1388 of file core_cm55.h.
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
Definition at line 1389 of file core_cm55.h.
| #define DWT_FUNCTION_ACTION_Pos 4U |
DWT FUNCTION: ACTION Position
Definition at line 1391 of file core_cm55.h.
| #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) |
DWT FUNCTION: ACTION Mask
Definition at line 1392 of file core_cm55.h.
| #define DWT_FUNCTION_MATCH_Pos 0U |
DWT FUNCTION: MATCH Position
Definition at line 1394 of file core_cm55.h.
| #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) |
DWT FUNCTION: MATCH Mask
Definition at line 1395 of file core_cm55.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 1885 of file core_cm55.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 1886 of file core_cm55.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 1889 of file core_cm55.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 1890 of file core_cm55.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 1892 of file core_cm55.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 1893 of file core_cm55.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 1895 of file core_cm55.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 1896 of file core_cm55.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 1898 of file core_cm55.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 1899 of file core_cm55.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 1902 of file core_cm55.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 1903 of file core_cm55.h.
| #define TPI_FFCR_FOnMan_Pos 6U |
TPI FFCR: FOnMan Position
Definition at line 1905 of file core_cm55.h.
| #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) |
TPI FFCR: FOnMan Mask
Definition at line 1906 of file core_cm55.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 1926 of file core_cm55.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1927 of file core_cm55.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 1929 of file core_cm55.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1930 of file core_cm55.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 1932 of file core_cm55.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1933 of file core_cm55.h.
| #define TPI_DEVID_FIFOSZ_Pos 6U |
TPI DEVID: FIFO depth Position
TPI DEVID: FIFOSZ Position
Definition at line 1935 of file core_cm55.h.
| #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) |
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
Definition at line 1939 of file core_cm55.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 1940 of file core_cm55.h.
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
Definition at line 1942 of file core_cm55.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1943 of file core_cm55.h.
| #define MPU_TYPE_IREGION_Pos 16U |
MPU TYPE: IREGION Position
Definition at line 2802 of file core_cm55.h.
| #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) |
MPU TYPE: IREGION Mask
Definition at line 2803 of file core_cm55.h.
| #define MPU_TYPE_DREGION_Pos 8U |
MPU TYPE: DREGION Position
Definition at line 2805 of file core_cm55.h.
| #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) |
MPU TYPE: DREGION Mask
Definition at line 2806 of file core_cm55.h.
| #define MPU_TYPE_SEPARATE_Pos 0U |
MPU TYPE: SEPARATE Position
Definition at line 2808 of file core_cm55.h.
| #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) |
MPU TYPE: SEPARATE Mask
Definition at line 2809 of file core_cm55.h.
| #define MPU_CTRL_PRIVDEFENA_Pos 2U |
MPU CTRL: PRIVDEFENA Position
Definition at line 2812 of file core_cm55.h.
| #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) |
MPU CTRL: PRIVDEFENA Mask
Definition at line 2813 of file core_cm55.h.
| #define MPU_CTRL_HFNMIENA_Pos 1U |
MPU CTRL: HFNMIENA Position
Definition at line 2815 of file core_cm55.h.
| #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) |
MPU CTRL: HFNMIENA Mask
Definition at line 2816 of file core_cm55.h.
| #define MPU_CTRL_ENABLE_Pos 0U |
MPU CTRL: ENABLE Position
Definition at line 2818 of file core_cm55.h.
| #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) |
MPU CTRL: ENABLE Mask
Definition at line 2819 of file core_cm55.h.
| #define MPU_RNR_REGION_Pos 0U |
MPU RNR: REGION Position
Definition at line 2822 of file core_cm55.h.
| #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) |
MPU RNR: REGION Mask
Definition at line 2823 of file core_cm55.h.
| #define MPU_RBAR_BASE_Pos 5U |
MPU RBAR: BASE Position
Definition at line 2826 of file core_cm55.h.
| #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) |
MPU RBAR: BASE Mask
Definition at line 2827 of file core_cm55.h.
| #define MPU_RBAR_SH_Pos 3U |
MPU RBAR: SH Position
Definition at line 2829 of file core_cm55.h.
| #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) |
MPU RBAR: SH Mask
Definition at line 2830 of file core_cm55.h.
| #define MPU_RBAR_AP_Pos 1U |
MPU RBAR: AP Position
Definition at line 2832 of file core_cm55.h.
| #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) |
MPU RBAR: AP Mask
Definition at line 2833 of file core_cm55.h.
| #define MPU_RBAR_XN_Pos 0U |
MPU RBAR: XN Position
Definition at line 2835 of file core_cm55.h.
| #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) |
MPU RBAR: XN Mask
Definition at line 2836 of file core_cm55.h.
| #define MPU_RLAR_LIMIT_Pos 5U |
MPU RLAR: LIMIT Position
Definition at line 2839 of file core_cm55.h.
| #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) |
MPU RLAR: LIMIT Mask
Definition at line 2840 of file core_cm55.h.
| #define MPU_RLAR_AttrIndx_Pos 1U |
MPU RLAR: AttrIndx Position
Definition at line 2845 of file core_cm55.h.
| #define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) |
MPU RLAR: AttrIndx Mask
Definition at line 2846 of file core_cm55.h.
| #define MPU_RLAR_EN_Pos 0U |
MPU RLAR: Region enable bit Position
Definition at line 2848 of file core_cm55.h.
| #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) |
MPU RLAR: Region enable bit Disable Mask
Definition at line 2849 of file core_cm55.h.
| #define MPU_MAIR0_Attr3_Pos 24U |
MPU MAIR0: Attr3 Position
Definition at line 2852 of file core_cm55.h.
| #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) |
MPU MAIR0: Attr3 Mask
Definition at line 2853 of file core_cm55.h.
| #define MPU_MAIR0_Attr2_Pos 16U |
MPU MAIR0: Attr2 Position
Definition at line 2855 of file core_cm55.h.
| #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) |
MPU MAIR0: Attr2 Mask
Definition at line 2856 of file core_cm55.h.
| #define MPU_MAIR0_Attr1_Pos 8U |
MPU MAIR0: Attr1 Position
Definition at line 2858 of file core_cm55.h.
| #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) |
MPU MAIR0: Attr1 Mask
Definition at line 2859 of file core_cm55.h.
| #define MPU_MAIR0_Attr0_Pos 0U |
MPU MAIR0: Attr0 Position
Definition at line 2861 of file core_cm55.h.
| #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) |
MPU MAIR0: Attr0 Mask
Definition at line 2862 of file core_cm55.h.
| #define MPU_MAIR1_Attr7_Pos 24U |
MPU MAIR1: Attr7 Position
Definition at line 2865 of file core_cm55.h.
| #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) |
MPU MAIR1: Attr7 Mask
Definition at line 2866 of file core_cm55.h.
| #define MPU_MAIR1_Attr6_Pos 16U |
MPU MAIR1: Attr6 Position
Definition at line 2868 of file core_cm55.h.
| #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) |
MPU MAIR1: Attr6 Mask
Definition at line 2869 of file core_cm55.h.
| #define MPU_MAIR1_Attr5_Pos 8U |
MPU MAIR1: Attr5 Position
Definition at line 2871 of file core_cm55.h.
| #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) |
MPU MAIR1: Attr5 Mask
Definition at line 2872 of file core_cm55.h.
| #define MPU_MAIR1_Attr4_Pos 0U |
MPU MAIR1: Attr4 Position
Definition at line 2874 of file core_cm55.h.
| #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) |
MPU MAIR1: Attr4 Mask
Definition at line 2875 of file core_cm55.h.
| #define FPU_FPCCR_ASPEN_Pos 31U |
FPCCR: ASPEN bit Position
Definition at line 2990 of file core_cm55.h.
| #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) |
FPCCR: ASPEN bit Mask
Definition at line 2991 of file core_cm55.h.
| #define FPU_FPCCR_LSPEN_Pos 30U |
FPCCR: LSPEN Position
Definition at line 2993 of file core_cm55.h.
| #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) |
FPCCR: LSPEN bit Mask
Definition at line 2994 of file core_cm55.h.
| #define FPU_FPCCR_LSPENS_Pos 29U |
FPCCR: LSPENS Position
Definition at line 2996 of file core_cm55.h.
| #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) |
FPCCR: LSPENS bit Mask
Definition at line 2997 of file core_cm55.h.
| #define FPU_FPCCR_CLRONRET_Pos 28U |
FPCCR: CLRONRET Position
Definition at line 2999 of file core_cm55.h.
| #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) |
FPCCR: CLRONRET bit Mask
Definition at line 3000 of file core_cm55.h.
| #define FPU_FPCCR_CLRONRETS_Pos 27U |
FPCCR: CLRONRETS Position
Definition at line 3002 of file core_cm55.h.
| #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) |
FPCCR: CLRONRETS bit Mask
Definition at line 3003 of file core_cm55.h.
| #define FPU_FPCCR_TS_Pos 26U |
FPCCR: TS Position
Definition at line 3005 of file core_cm55.h.
| #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) |
FPCCR: TS bit Mask
Definition at line 3006 of file core_cm55.h.
| #define FPU_FPCCR_UFRDY_Pos 10U |
FPCCR: UFRDY Position
Definition at line 3008 of file core_cm55.h.
| #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) |
FPCCR: UFRDY bit Mask
Definition at line 3009 of file core_cm55.h.
| #define FPU_FPCCR_SPLIMVIOL_Pos 9U |
FPCCR: SPLIMVIOL Position
Definition at line 3011 of file core_cm55.h.
| #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) |
FPCCR: SPLIMVIOL bit Mask
Definition at line 3012 of file core_cm55.h.
| #define FPU_FPCCR_MONRDY_Pos 8U |
FPCCR: MONRDY Position
Definition at line 3014 of file core_cm55.h.
| #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) |
FPCCR: MONRDY bit Mask
Definition at line 3015 of file core_cm55.h.
| #define FPU_FPCCR_SFRDY_Pos 7U |
FPCCR: SFRDY Position
Definition at line 3017 of file core_cm55.h.
| #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) |
FPCCR: SFRDY bit Mask
Definition at line 3018 of file core_cm55.h.
| #define FPU_FPCCR_BFRDY_Pos 6U |
FPCCR: BFRDY Position
Definition at line 3020 of file core_cm55.h.
| #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) |
FPCCR: BFRDY bit Mask
Definition at line 3021 of file core_cm55.h.
| #define FPU_FPCCR_MMRDY_Pos 5U |
FPCCR: MMRDY Position
Definition at line 3023 of file core_cm55.h.
| #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) |
FPCCR: MMRDY bit Mask
Definition at line 3024 of file core_cm55.h.
| #define FPU_FPCCR_HFRDY_Pos 4U |
FPCCR: HFRDY Position
Definition at line 3026 of file core_cm55.h.
| #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) |
FPCCR: HFRDY bit Mask
Definition at line 3027 of file core_cm55.h.
| #define FPU_FPCCR_THREAD_Pos 3U |
FPCCR: processor mode bit Position
Definition at line 3029 of file core_cm55.h.
| #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) |
FPCCR: processor mode active bit Mask
Definition at line 3030 of file core_cm55.h.
| #define FPU_FPCCR_S_Pos 2U |
FPCCR: Security status of the FP context bit Position
Definition at line 3032 of file core_cm55.h.
| #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) |
FPCCR: Security status of the FP context bit Mask
Definition at line 3033 of file core_cm55.h.
| #define FPU_FPCCR_USER_Pos 1U |
FPCCR: privilege level bit Position
Definition at line 3035 of file core_cm55.h.
| #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) |
FPCCR: privilege level bit Mask
Definition at line 3036 of file core_cm55.h.
| #define FPU_FPCCR_LSPACT_Pos 0U |
FPCCR: Lazy state preservation active bit Position
Definition at line 3038 of file core_cm55.h.
| #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) |
FPCCR: Lazy state preservation active bit Mask
Definition at line 3039 of file core_cm55.h.
| #define FPU_FPCAR_ADDRESS_Pos 3U |
FPCAR: ADDRESS bit Position
Definition at line 3042 of file core_cm55.h.
| #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) |
FPCAR: ADDRESS bit Mask
Definition at line 3043 of file core_cm55.h.
| #define FPU_FPDSCR_AHP_Pos 26U |
FPDSCR: AHP bit Position
Definition at line 3046 of file core_cm55.h.
| #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) |
FPDSCR: AHP bit Mask
Definition at line 3047 of file core_cm55.h.
| #define FPU_FPDSCR_DN_Pos 25U |
FPDSCR: DN bit Position
Definition at line 3049 of file core_cm55.h.
| #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) |
FPDSCR: DN bit Mask
Definition at line 3050 of file core_cm55.h.
| #define FPU_FPDSCR_FZ_Pos 24U |
FPDSCR: FZ bit Position
Definition at line 3052 of file core_cm55.h.
| #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) |
FPDSCR: FZ bit Mask
Definition at line 3053 of file core_cm55.h.
| #define FPU_FPDSCR_RMode_Pos 22U |
FPDSCR: RMode bit Position
Definition at line 3055 of file core_cm55.h.
| #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) |
FPDSCR: RMode bit Mask
Definition at line 3056 of file core_cm55.h.
| #define FPU_MVFR2_FPMisc_Pos 4U |
MVFR2: FPMisc bits Position
Definition at line 3103 of file core_cm55.h.
| #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) |
MVFR2: FPMisc bits Mask
Definition at line 3104 of file core_cm55.h.
| #define DCB_DHCSR_DBGKEY_Pos 16U |
DCB DHCSR: Debug key Position
Definition at line 3302 of file core_cm55.h.
| #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) |
DCB DHCSR: Debug key Mask
Definition at line 3303 of file core_cm55.h.
| #define DCB_DHCSR_S_RESTART_ST_Pos 26U |
DCB DHCSR: Restart sticky status Position
Definition at line 3305 of file core_cm55.h.
| #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) |
DCB DHCSR: Restart sticky status Mask
Definition at line 3306 of file core_cm55.h.
| #define DCB_DHCSR_S_RESET_ST_Pos 25U |
DCB DHCSR: Reset sticky status Position
Definition at line 3308 of file core_cm55.h.
| #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) |
DCB DHCSR: Reset sticky status Mask
Definition at line 3309 of file core_cm55.h.
| #define DCB_DHCSR_S_RETIRE_ST_Pos 24U |
DCB DHCSR: Retire sticky status Position
Definition at line 3311 of file core_cm55.h.
| #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) |
DCB DHCSR: Retire sticky status Mask
Definition at line 3312 of file core_cm55.h.
| #define DCB_DHCSR_S_SDE_Pos 20U |
DCB DHCSR: Secure debug enabled Position
Definition at line 3323 of file core_cm55.h.
| #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) |
DCB DHCSR: Secure debug enabled Mask
Definition at line 3324 of file core_cm55.h.
| #define DCB_DHCSR_S_LOCKUP_Pos 19U |
DCB DHCSR: Lockup status Position
Definition at line 3326 of file core_cm55.h.
| #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) |
DCB DHCSR: Lockup status Mask
Definition at line 3327 of file core_cm55.h.
| #define DCB_DHCSR_S_SLEEP_Pos 18U |
DCB DHCSR: Sleeping status Position
Definition at line 3329 of file core_cm55.h.
| #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) |
DCB DHCSR: Sleeping status Mask
Definition at line 3330 of file core_cm55.h.
| #define DCB_DHCSR_S_HALT_Pos 17U |
DCB DHCSR: Halted status Position
Definition at line 3332 of file core_cm55.h.
| #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) |
DCB DHCSR: Halted status Mask
Definition at line 3333 of file core_cm55.h.
| #define DCB_DHCSR_S_REGRDY_Pos 16U |
DCB DHCSR: Register ready status Position
Definition at line 3335 of file core_cm55.h.
| #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) |
DCB DHCSR: Register ready status Mask
Definition at line 3336 of file core_cm55.h.
| #define DCB_DHCSR_C_SNAPSTALL_Pos 5U |
DCB DHCSR: Snap stall control Position
Definition at line 3341 of file core_cm55.h.
| #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) |
DCB DHCSR: Snap stall control Mask
Definition at line 3342 of file core_cm55.h.
| #define DCB_DHCSR_C_MASKINTS_Pos 3U |
DCB DHCSR: Mask interrupts control Position
Definition at line 3344 of file core_cm55.h.
| #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) |
DCB DHCSR: Mask interrupts control Mask
Definition at line 3345 of file core_cm55.h.
| #define DCB_DHCSR_C_STEP_Pos 2U |
DCB DHCSR: Step control Position
Definition at line 3347 of file core_cm55.h.
| #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) |
DCB DHCSR: Step control Mask
Definition at line 3348 of file core_cm55.h.
| #define DCB_DHCSR_C_HALT_Pos 1U |
DCB DHCSR: Halt control Position
Definition at line 3350 of file core_cm55.h.
| #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) |
DCB DHCSR: Halt control Mask
Definition at line 3351 of file core_cm55.h.
| #define DCB_DHCSR_C_DEBUGEN_Pos 0U |
DCB DHCSR: Debug enable control Position
Definition at line 3353 of file core_cm55.h.
| #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) |
DCB DHCSR: Debug enable control Mask
Definition at line 3354 of file core_cm55.h.
| #define DCB_DCRSR_REGWnR_Pos 16U |
DCB DCRSR: Register write/not-read Position
Definition at line 3357 of file core_cm55.h.
| #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) |
DCB DCRSR: Register write/not-read Mask
Definition at line 3358 of file core_cm55.h.
| #define DCB_DCRSR_REGSEL_Pos 0U |
DCB DCRSR: Register selector Position
Definition at line 3360 of file core_cm55.h.
| #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) |
DCB DCRSR: Register selector Mask
Definition at line 3361 of file core_cm55.h.
| #define DCB_DCRDR_DBGTMP_Pos 0U |
DCB DCRDR: Data temporary buffer Position
Definition at line 3364 of file core_cm55.h.
| #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) |
DCB DCRDR: Data temporary buffer Mask
Definition at line 3365 of file core_cm55.h.
| #define DCB_DEMCR_TRCENA_Pos 24U |
DCB DEMCR: Trace enable Position
Definition at line 3368 of file core_cm55.h.
| #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) |
DCB DEMCR: Trace enable Mask
Definition at line 3369 of file core_cm55.h.
| #define DCB_DEMCR_MONPRKEY_Pos 23U |
DCB DEMCR: Monitor pend req key Position
Definition at line 3371 of file core_cm55.h.
| #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) |
DCB DEMCR: Monitor pend req key Mask
Definition at line 3372 of file core_cm55.h.
| #define DCB_DEMCR_UMON_EN_Pos 21U |
DCB DEMCR: Unprivileged monitor enable Position
Definition at line 3374 of file core_cm55.h.
| #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) |
DCB DEMCR: Unprivileged monitor enable Mask
Definition at line 3375 of file core_cm55.h.
| #define DCB_DEMCR_SDME_Pos 20U |
DCB DEMCR: Secure DebugMonitor enable Position
Definition at line 3377 of file core_cm55.h.
| #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) |
DCB DEMCR: Secure DebugMonitor enable Mask
Definition at line 3378 of file core_cm55.h.
| #define DCB_DEMCR_MON_REQ_Pos 19U |
DCB DEMCR: Monitor request Position
Definition at line 3380 of file core_cm55.h.
| #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) |
DCB DEMCR: Monitor request Mask
Definition at line 3381 of file core_cm55.h.
| #define DCB_DEMCR_MON_STEP_Pos 18U |
DCB DEMCR: Monitor step Position
Definition at line 3383 of file core_cm55.h.
| #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) |
DCB DEMCR: Monitor step Mask
Definition at line 3384 of file core_cm55.h.
| #define DCB_DEMCR_MON_PEND_Pos 17U |
DCB DEMCR: Monitor pend Position
Definition at line 3386 of file core_cm55.h.
| #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) |
DCB DEMCR: Monitor pend Mask
Definition at line 3387 of file core_cm55.h.
| #define DCB_DEMCR_MON_EN_Pos 16U |
DCB DEMCR: Monitor enable Position
Definition at line 3389 of file core_cm55.h.
| #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) |
DCB DEMCR: Monitor enable Mask
Definition at line 3390 of file core_cm55.h.
| #define DCB_DEMCR_VC_SFERR_Pos 11U |
DCB DEMCR: Vector Catch SecureFault Position
Definition at line 3392 of file core_cm55.h.
| #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) |
DCB DEMCR: Vector Catch SecureFault Mask
Definition at line 3393 of file core_cm55.h.
| #define DCB_DEMCR_VC_HARDERR_Pos 10U |
DCB DEMCR: Vector Catch HardFault errors Position
Definition at line 3395 of file core_cm55.h.
| #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) |
DCB DEMCR: Vector Catch HardFault errors Mask
Definition at line 3396 of file core_cm55.h.
| #define DCB_DEMCR_VC_INTERR_Pos 9U |
DCB DEMCR: Vector Catch interrupt errors Position
Definition at line 3398 of file core_cm55.h.
| #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) |
DCB DEMCR: Vector Catch interrupt errors Mask
Definition at line 3399 of file core_cm55.h.
| #define DCB_DEMCR_VC_BUSERR_Pos 8U |
DCB DEMCR: Vector Catch BusFault errors Position
Definition at line 3401 of file core_cm55.h.
| #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) |
DCB DEMCR: Vector Catch BusFault errors Mask
Definition at line 3402 of file core_cm55.h.
| #define DCB_DEMCR_VC_STATERR_Pos 7U |
DCB DEMCR: Vector Catch state errors Position
Definition at line 3404 of file core_cm55.h.
| #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) |
DCB DEMCR: Vector Catch state errors Mask
Definition at line 3405 of file core_cm55.h.
| #define DCB_DEMCR_VC_CHKERR_Pos 6U |
DCB DEMCR: Vector Catch check errors Position
Definition at line 3407 of file core_cm55.h.
| #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) |
DCB DEMCR: Vector Catch check errors Mask
Definition at line 3408 of file core_cm55.h.
| #define DCB_DEMCR_VC_NOCPERR_Pos 5U |
DCB DEMCR: Vector Catch NOCP errors Position
Definition at line 3410 of file core_cm55.h.
| #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) |
DCB DEMCR: Vector Catch NOCP errors Mask
Definition at line 3411 of file core_cm55.h.
| #define DCB_DEMCR_VC_MMERR_Pos 4U |
DCB DEMCR: Vector Catch MemManage errors Position
Definition at line 3413 of file core_cm55.h.
| #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) |
DCB DEMCR: Vector Catch MemManage errors Mask
Definition at line 3414 of file core_cm55.h.
| #define DCB_DEMCR_VC_CORERESET_Pos 0U |
DCB DEMCR: Vector Catch Core reset Position
Definition at line 3416 of file core_cm55.h.
| #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) |
DCB DEMCR: Vector Catch Core reset Mask
Definition at line 3417 of file core_cm55.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position
Definition at line 3442 of file core_cm55.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask
Definition at line 3443 of file core_cm55.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U |
DCB DAUTHCTRL: Secure non-invasive debug enable select Position
Definition at line 3445 of file core_cm55.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) |
DCB DAUTHCTRL: Secure non-invasive debug enable select Mask
Definition at line 3446 of file core_cm55.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U |
DCB DAUTHCTRL: Internal Secure invasive debug enable Position
Definition at line 3448 of file core_cm55.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure invasive debug enable Mask
Definition at line 3449 of file core_cm55.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U |
DCB DAUTHCTRL: Secure invasive debug enable select Position
Definition at line 3451 of file core_cm55.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) |
DCB DAUTHCTRL: Secure invasive debug enable select Mask
Definition at line 3452 of file core_cm55.h.
| #define DCB_DSCSR_CDSKEY_Pos 17U |
DCB DSCSR: CDS write-enable key Position
Definition at line 3455 of file core_cm55.h.
| #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) |
DCB DSCSR: CDS write-enable key Mask
Definition at line 3456 of file core_cm55.h.
| #define DCB_DSCSR_CDS_Pos 16U |
DCB DSCSR: Current domain Secure Position
Definition at line 3458 of file core_cm55.h.
| #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) |
DCB DSCSR: Current domain Secure Mask
Definition at line 3459 of file core_cm55.h.
| #define DCB_DSCSR_SBRSEL_Pos 1U |
DCB DSCSR: Secure banked register select Position
Definition at line 3461 of file core_cm55.h.
| #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) |
DCB DSCSR: Secure banked register select Mask
Definition at line 3462 of file core_cm55.h.
| #define DCB_DSCSR_SBRSELEN_Pos 0U |
DCB DSCSR: Secure banked register select enable Position
Definition at line 3464 of file core_cm55.h.
| #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) |
DCB DSCSR: Secure banked register select enable Mask
Definition at line 3465 of file core_cm55.h.
| #define DIB_DLAR_KEY_Pos 0U |
DIB DLAR: KEY Position
Definition at line 3491 of file core_cm55.h.
| #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) |
DIB DLAR: KEY Mask
Definition at line 3492 of file core_cm55.h.
| #define DIB_DLSR_nTT_Pos 2U |
DIB DLSR: Not thirty-two bit Position
Definition at line 3495 of file core_cm55.h.
| #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) |
DIB DLSR: Not thirty-two bit Mask
Definition at line 3496 of file core_cm55.h.
| #define DIB_DLSR_SLK_Pos 1U |
DIB DLSR: Software Lock status Position
Definition at line 3498 of file core_cm55.h.
| #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) |
DIB DLSR: Software Lock status Mask
Definition at line 3499 of file core_cm55.h.
| #define DIB_DLSR_SLI_Pos 0U |
DIB DLSR: Software Lock implemented Position
Definition at line 3501 of file core_cm55.h.
| #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) |
DIB DLSR: Software Lock implemented Mask
Definition at line 3502 of file core_cm55.h.
| #define DIB_DAUTHSTATUS_SNID_Pos 6U |
DIB DAUTHSTATUS: Secure Non-invasive Debug Position
Definition at line 3517 of file core_cm55.h.
| #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) |
DIB DAUTHSTATUS: Secure Non-invasive Debug Mask
Definition at line 3518 of file core_cm55.h.
| #define DIB_DAUTHSTATUS_SID_Pos 4U |
DIB DAUTHSTATUS: Secure Invasive Debug Position
Definition at line 3520 of file core_cm55.h.
| #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) |
DIB DAUTHSTATUS: Secure Invasive Debug Mask
Definition at line 3521 of file core_cm55.h.
| #define DIB_DAUTHSTATUS_NSNID_Pos 2U |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position
Definition at line 3523 of file core_cm55.h.
| #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask
Definition at line 3524 of file core_cm55.h.
| #define DIB_DAUTHSTATUS_NSID_Pos 0U |
DIB DAUTHSTATUS: Non-secure Invasive Debug Position
Definition at line 3526 of file core_cm55.h.
| #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) |
DIB DAUTHSTATUS: Non-secure Invasive Debug Mask
Definition at line 3527 of file core_cm55.h.
| #define DIB_DDEVARCH_ARCHITECT_Pos 21U |
DIB DDEVARCH: Architect Position
Definition at line 3530 of file core_cm55.h.
| #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) |
DIB DDEVARCH: Architect Mask
Definition at line 3531 of file core_cm55.h.
| #define DIB_DDEVARCH_PRESENT_Pos 20U |
DIB DDEVARCH: DEVARCH Present Position
Definition at line 3533 of file core_cm55.h.
| #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) |
DIB DDEVARCH: DEVARCH Present Mask
Definition at line 3534 of file core_cm55.h.
| #define DIB_DDEVARCH_REVISION_Pos 16U |
DIB DDEVARCH: Revision Position
Definition at line 3536 of file core_cm55.h.
| #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) |
DIB DDEVARCH: Revision Mask
Definition at line 3537 of file core_cm55.h.
| #define DIB_DDEVARCH_ARCHVER_Pos 12U |
DIB DDEVARCH: Architecture Version Position
Definition at line 3539 of file core_cm55.h.
| #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) |
DIB DDEVARCH: Architecture Version Mask
Definition at line 3540 of file core_cm55.h.
| #define DIB_DDEVARCH_ARCHPART_Pos 0U |
DIB DDEVARCH: Architecture Part Position
Definition at line 3542 of file core_cm55.h.
| #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) |
DIB DDEVARCH: Architecture Part Mask
Definition at line 3543 of file core_cm55.h.
| #define DIB_DDEVTYPE_SUB_Pos 4U |
DIB DDEVTYPE: Sub-type Position
Definition at line 3546 of file core_cm55.h.
| #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) |
DIB DDEVTYPE: Sub-type Mask
Definition at line 3547 of file core_cm55.h.
| #define DIB_DDEVTYPE_MAJOR_Pos 0U |
DIB DDEVTYPE: Major type Position
Definition at line 3549 of file core_cm55.h.
| #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) |
DIB DDEVTYPE: Major type Mask
Definition at line 3550 of file core_cm55.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 3569 of file core_cm55.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 3577 of file core_cm55.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 3590 of file core_cm55.h.
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
Definition at line 3591 of file core_cm55.h.
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
Definition at line 3592 of file core_cm55.h.
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
Definition at line 3599 of file core_cm55.h.
| #define DCB_BASE (0xE000EDF0UL) |
DCB Base Address
Definition at line 3601 of file core_cm55.h.
| #define DIB_BASE (0xE000EFB0UL) |
DIB Base Address
Definition at line 3602 of file core_cm55.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 3603 of file core_cm55.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 3604 of file core_cm55.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 3605 of file core_cm55.h.
SCB configuration struct
Definition at line 3608 of file core_cm55.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 3609 of file core_cm55.h.
NVIC configuration struct
Definition at line 3610 of file core_cm55.h.
ITM configuration struct
Definition at line 3611 of file core_cm55.h.
DWT configuration struct
Definition at line 3612 of file core_cm55.h.
TPI configuration struct
Definition at line 3613 of file core_cm55.h.
DCB configuration struct
Definition at line 3621 of file core_cm55.h.
DIB configuration struct
Definition at line 3622 of file core_cm55.h.
| #define MPU_BASE (SCS_BASE + 0x0D90UL) |
Memory Protection Unit
Definition at line 3625 of file core_cm55.h.
Memory Protection Unit
Definition at line 3626 of file core_cm55.h.
| #define FPU_BASE (SCS_BASE + 0x0F30UL) |
Floating Point Unit
Definition at line 3639 of file core_cm55.h.
Floating Point Unit
Definition at line 3640 of file core_cm55.h.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 4741 of file core_cm55.h.
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
Definition at line 444 of file core_cm7.h.
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
Definition at line 445 of file core_cm7.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 516 of file core_cm7.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 517 of file core_cm7.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 519 of file core_cm7.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 520 of file core_cm7.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 522 of file core_cm7.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 523 of file core_cm7.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 525 of file core_cm7.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 526 of file core_cm7.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 528 of file core_cm7.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 529 of file core_cm7.h.
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
Definition at line 532 of file core_cm7.h.
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
Definition at line 533 of file core_cm7.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 535 of file core_cm7.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 536 of file core_cm7.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 538 of file core_cm7.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 539 of file core_cm7.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 541 of file core_cm7.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 542 of file core_cm7.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 544 of file core_cm7.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 545 of file core_cm7.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 547 of file core_cm7.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 548 of file core_cm7.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 550 of file core_cm7.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 551 of file core_cm7.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 553 of file core_cm7.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 554 of file core_cm7.h.
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
Definition at line 556 of file core_cm7.h.
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
Definition at line 557 of file core_cm7.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 559 of file core_cm7.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 560 of file core_cm7.h.
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
Definition at line 563 of file core_cm7.h.
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
Definition at line 564 of file core_cm7.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 567 of file core_cm7.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 568 of file core_cm7.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 570 of file core_cm7.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 571 of file core_cm7.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 573 of file core_cm7.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 574 of file core_cm7.h.
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
Definition at line 576 of file core_cm7.h.
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
Definition at line 577 of file core_cm7.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 579 of file core_cm7.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 580 of file core_cm7.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 582 of file core_cm7.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 583 of file core_cm7.h.
| #define SCB_AIRCR_VECTRESET_Pos 0U |
SCB AIRCR: VECTRESET Position
Definition at line 585 of file core_cm7.h.
| #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) |
SCB AIRCR: VECTRESET Mask
Definition at line 586 of file core_cm7.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 589 of file core_cm7.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 590 of file core_cm7.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 592 of file core_cm7.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 593 of file core_cm7.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 595 of file core_cm7.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 596 of file core_cm7.h.
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: Branch prediction enable bit Position
SCB CCR: BP Position
Definition at line 599 of file core_cm7.h.
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: Branch prediction enable bit Mask
SCB CCR: BP Mask
Definition at line 600 of file core_cm7.h.
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: Instruction cache enable bit Position
SCB CCR: IC Position
Definition at line 602 of file core_cm7.h.
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: Instruction cache enable bit Mask
SCB CCR: IC Mask
Definition at line 603 of file core_cm7.h.
| #define SCB_CCR_DC_Pos 16U |
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
Definition at line 608 of file core_cm7.h.
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
Definition at line 609 of file core_cm7.h.
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
Definition at line 611 of file core_cm7.h.
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
Definition at line 612 of file core_cm7.h.
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
Definition at line 614 of file core_cm7.h.
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
Definition at line 615 of file core_cm7.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 617 of file core_cm7.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 618 of file core_cm7.h.
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
Definition at line 620 of file core_cm7.h.
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
Definition at line 621 of file core_cm7.h.
| #define SCB_CCR_NONBASETHRDENA_Pos 0U |
SCB CCR: NONBASETHRDENA Position
Definition at line 623 of file core_cm7.h.
| #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) |
SCB CCR: NONBASETHRDENA Mask
Definition at line 624 of file core_cm7.h.
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
Definition at line 627 of file core_cm7.h.
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
Definition at line 628 of file core_cm7.h.
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
Definition at line 630 of file core_cm7.h.
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
Definition at line 631 of file core_cm7.h.
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
Definition at line 633 of file core_cm7.h.
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
Definition at line 634 of file core_cm7.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 636 of file core_cm7.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 637 of file core_cm7.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
Definition at line 639 of file core_cm7.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
Definition at line 640 of file core_cm7.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
Definition at line 642 of file core_cm7.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
Definition at line 643 of file core_cm7.h.
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
Definition at line 645 of file core_cm7.h.
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
Definition at line 646 of file core_cm7.h.
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
Definition at line 648 of file core_cm7.h.
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
Definition at line 649 of file core_cm7.h.
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
Definition at line 651 of file core_cm7.h.
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
Definition at line 652 of file core_cm7.h.
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
Definition at line 654 of file core_cm7.h.
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
Definition at line 655 of file core_cm7.h.
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
Definition at line 657 of file core_cm7.h.
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
Definition at line 658 of file core_cm7.h.
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
Definition at line 660 of file core_cm7.h.
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
Definition at line 661 of file core_cm7.h.
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
Definition at line 663 of file core_cm7.h.
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
Definition at line 664 of file core_cm7.h.
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
Definition at line 666 of file core_cm7.h.
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
Definition at line 667 of file core_cm7.h.
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
Definition at line 670 of file core_cm7.h.
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
Definition at line 671 of file core_cm7.h.
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
Definition at line 673 of file core_cm7.h.
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
Definition at line 674 of file core_cm7.h.
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
Definition at line 676 of file core_cm7.h.
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
Definition at line 677 of file core_cm7.h.
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
Definition at line 680 of file core_cm7.h.
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
Definition at line 681 of file core_cm7.h.
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
Definition at line 683 of file core_cm7.h.
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
Definition at line 684 of file core_cm7.h.
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
Definition at line 686 of file core_cm7.h.
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
Definition at line 687 of file core_cm7.h.
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
Definition at line 689 of file core_cm7.h.
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
Definition at line 690 of file core_cm7.h.
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
Definition at line 692 of file core_cm7.h.
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
Definition at line 693 of file core_cm7.h.
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
Definition at line 695 of file core_cm7.h.
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
Definition at line 696 of file core_cm7.h.
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
Definition at line 699 of file core_cm7.h.
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
Definition at line 700 of file core_cm7.h.
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
Definition at line 702 of file core_cm7.h.
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
Definition at line 703 of file core_cm7.h.
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
Definition at line 705 of file core_cm7.h.
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
Definition at line 706 of file core_cm7.h.
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
Definition at line 708 of file core_cm7.h.
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
Definition at line 709 of file core_cm7.h.
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
Definition at line 711 of file core_cm7.h.
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
Definition at line 712 of file core_cm7.h.
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
Definition at line 714 of file core_cm7.h.
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
Definition at line 715 of file core_cm7.h.
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
Definition at line 717 of file core_cm7.h.
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
Definition at line 718 of file core_cm7.h.
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
Definition at line 721 of file core_cm7.h.
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
Definition at line 722 of file core_cm7.h.
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
Definition at line 724 of file core_cm7.h.
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
Definition at line 725 of file core_cm7.h.
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
Definition at line 727 of file core_cm7.h.
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
Definition at line 728 of file core_cm7.h.
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
Definition at line 730 of file core_cm7.h.
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
Definition at line 731 of file core_cm7.h.
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
Definition at line 733 of file core_cm7.h.
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
Definition at line 734 of file core_cm7.h.
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
Definition at line 736 of file core_cm7.h.
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
Definition at line 737 of file core_cm7.h.
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
Definition at line 740 of file core_cm7.h.
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
Definition at line 741 of file core_cm7.h.
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
Definition at line 743 of file core_cm7.h.
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
Definition at line 744 of file core_cm7.h.
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
Definition at line 746 of file core_cm7.h.
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
Definition at line 747 of file core_cm7.h.
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
Definition at line 750 of file core_cm7.h.
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
Definition at line 751 of file core_cm7.h.
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
Definition at line 753 of file core_cm7.h.
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
Definition at line 754 of file core_cm7.h.
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
Definition at line 756 of file core_cm7.h.
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
Definition at line 757 of file core_cm7.h.
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
Definition at line 759 of file core_cm7.h.
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
Definition at line 760 of file core_cm7.h.
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
Definition at line 762 of file core_cm7.h.
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
Definition at line 763 of file core_cm7.h.
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
Definition at line 766 of file core_cm7.h.
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
Definition at line 767 of file core_cm7.h.
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
Definition at line 769 of file core_cm7.h.
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
Definition at line 770 of file core_cm7.h.
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
Definition at line 773 of file core_cm7.h.
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
Definition at line 774 of file core_cm7.h.
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
Definition at line 776 of file core_cm7.h.
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
Definition at line 777 of file core_cm7.h.
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
Definition at line 779 of file core_cm7.h.
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
Definition at line 780 of file core_cm7.h.
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
Definition at line 782 of file core_cm7.h.
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
Definition at line 783 of file core_cm7.h.
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
Definition at line 785 of file core_cm7.h.
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
Definition at line 786 of file core_cm7.h.
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
Definition at line 789 of file core_cm7.h.
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
Definition at line 790 of file core_cm7.h.
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
Definition at line 792 of file core_cm7.h.
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
Definition at line 793 of file core_cm7.h.
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
Definition at line 795 of file core_cm7.h.
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
Definition at line 796 of file core_cm7.h.
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
Definition at line 798 of file core_cm7.h.
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
Definition at line 799 of file core_cm7.h.
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
Definition at line 801 of file core_cm7.h.
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
Definition at line 802 of file core_cm7.h.
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
Definition at line 804 of file core_cm7.h.
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
Definition at line 805 of file core_cm7.h.
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
Definition at line 807 of file core_cm7.h.
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
Definition at line 808 of file core_cm7.h.
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
Definition at line 811 of file core_cm7.h.
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
Definition at line 812 of file core_cm7.h.
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
Definition at line 814 of file core_cm7.h.
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
Definition at line 815 of file core_cm7.h.
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
Definition at line 818 of file core_cm7.h.
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
Definition at line 819 of file core_cm7.h.
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
Definition at line 822 of file core_cm7.h.
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
Definition at line 823 of file core_cm7.h.
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
Definition at line 825 of file core_cm7.h.
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
Definition at line 826 of file core_cm7.h.
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
Definition at line 829 of file core_cm7.h.
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
Definition at line 830 of file core_cm7.h.
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
Definition at line 832 of file core_cm7.h.
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
Definition at line 833 of file core_cm7.h.
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
Definition at line 836 of file core_cm7.h.
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
Definition at line 837 of file core_cm7.h.
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
Definition at line 839 of file core_cm7.h.
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
Definition at line 840 of file core_cm7.h.
| #define SCB_ITCMCR_SZ_Pos 3U |
SCB ITCMCR: SZ Position
Definition at line 843 of file core_cm7.h.
| #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) |
SCB ITCMCR: SZ Mask
Definition at line 844 of file core_cm7.h.
| #define SCB_ITCMCR_EN_Pos 0U |
SCB ITCMCR: EN Position
Definition at line 852 of file core_cm7.h.
| #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) |
SCB ITCMCR: EN Mask
Definition at line 853 of file core_cm7.h.
| #define SCB_DTCMCR_SZ_Pos 3U |
SCB DTCMCR: SZ Position
Definition at line 856 of file core_cm7.h.
| #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) |
SCB DTCMCR: SZ Mask
Definition at line 857 of file core_cm7.h.
| #define SCB_DTCMCR_EN_Pos 0U |
SCB DTCMCR: EN Position
Definition at line 865 of file core_cm7.h.
| #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) |
SCB DTCMCR: EN Mask
Definition at line 866 of file core_cm7.h.
| #define SCB_CACR_FORCEWT_Pos 2U |
SCB CACR: FORCEWT Position
Definition at line 876 of file core_cm7.h.
| #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
SCB CACR: FORCEWT Mask
Definition at line 877 of file core_cm7.h.
| #define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
Definition at line 938 of file core_cm7.h.
| #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
Definition at line 939 of file core_cm7.h.
| #define SCnSCB_ACTLR_DISFOLD_Pos 2U |
ACTLR: DISFOLD Position
Definition at line 969 of file core_cm7.h.
| #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) |
ACTLR: DISFOLD Mask
Definition at line 970 of file core_cm7.h.
| #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U |
ACTLR: DISMCYCINT Position
Definition at line 972 of file core_cm7.h.
| #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) |
ACTLR: DISMCYCINT Mask
Definition at line 973 of file core_cm7.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 997 of file core_cm7.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 998 of file core_cm7.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 1000 of file core_cm7.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 1001 of file core_cm7.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 1003 of file core_cm7.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 1004 of file core_cm7.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 1006 of file core_cm7.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 1007 of file core_cm7.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 1010 of file core_cm7.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 1011 of file core_cm7.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 1014 of file core_cm7.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 1015 of file core_cm7.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 1018 of file core_cm7.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 1019 of file core_cm7.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 1021 of file core_cm7.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 1022 of file core_cm7.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 1024 of file core_cm7.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 1025 of file core_cm7.h.
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
Definition at line 1074 of file core_cm7.h.
| #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
Definition at line 1075 of file core_cm7.h.
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
Definition at line 1078 of file core_cm7.h.
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
Definition at line 1079 of file core_cm7.h.
| #define ITM_TCR_TraceBusID_Pos 16U |
ITM TCR: ATBID Position
Definition at line 1081 of file core_cm7.h.
| #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) |
ITM TCR: ATBID Mask
Definition at line 1082 of file core_cm7.h.
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
Definition at line 1084 of file core_cm7.h.
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
Definition at line 1085 of file core_cm7.h.
| #define ITM_TCR_TSPrescale_Pos 8U |
ITM TCR: TSPrescale Position
Definition at line 1087 of file core_cm7.h.
| #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) |
ITM TCR: TSPrescale Mask
Definition at line 1088 of file core_cm7.h.
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
Definition at line 1090 of file core_cm7.h.
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
Definition at line 1091 of file core_cm7.h.
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
Definition at line 1093 of file core_cm7.h.
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
Definition at line 1094 of file core_cm7.h.
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
Definition at line 1096 of file core_cm7.h.
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
Definition at line 1097 of file core_cm7.h.
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
Definition at line 1099 of file core_cm7.h.
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
Definition at line 1100 of file core_cm7.h.
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
Definition at line 1102 of file core_cm7.h.
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
Definition at line 1103 of file core_cm7.h.
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
Definition at line 1106 of file core_cm7.h.
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
Definition at line 1107 of file core_cm7.h.
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
Definition at line 1109 of file core_cm7.h.
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
Definition at line 1110 of file core_cm7.h.
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
Definition at line 1112 of file core_cm7.h.
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
Definition at line 1113 of file core_cm7.h.
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
Definition at line 1159 of file core_cm7.h.
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
Definition at line 1160 of file core_cm7.h.
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
Definition at line 1162 of file core_cm7.h.
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
Definition at line 1163 of file core_cm7.h.
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
Definition at line 1165 of file core_cm7.h.
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
Definition at line 1166 of file core_cm7.h.
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
Definition at line 1168 of file core_cm7.h.
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
Definition at line 1169 of file core_cm7.h.
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
Definition at line 1171 of file core_cm7.h.
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
Definition at line 1172 of file core_cm7.h.
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
Definition at line 1174 of file core_cm7.h.
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
Definition at line 1175 of file core_cm7.h.
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
Definition at line 1177 of file core_cm7.h.
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
Definition at line 1178 of file core_cm7.h.
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
Definition at line 1180 of file core_cm7.h.
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
Definition at line 1181 of file core_cm7.h.
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
Definition at line 1183 of file core_cm7.h.
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
Definition at line 1184 of file core_cm7.h.
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
Definition at line 1186 of file core_cm7.h.
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
Definition at line 1187 of file core_cm7.h.
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
Definition at line 1189 of file core_cm7.h.
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
Definition at line 1190 of file core_cm7.h.
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
Definition at line 1192 of file core_cm7.h.
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
Definition at line 1193 of file core_cm7.h.
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
Definition at line 1195 of file core_cm7.h.
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
Definition at line 1196 of file core_cm7.h.
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
Definition at line 1198 of file core_cm7.h.
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
Definition at line 1199 of file core_cm7.h.
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
Definition at line 1201 of file core_cm7.h.
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
Definition at line 1202 of file core_cm7.h.
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
Definition at line 1204 of file core_cm7.h.
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
Definition at line 1205 of file core_cm7.h.
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
Definition at line 1207 of file core_cm7.h.
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
Definition at line 1208 of file core_cm7.h.
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
Definition at line 1210 of file core_cm7.h.
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
Definition at line 1211 of file core_cm7.h.
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
Definition at line 1214 of file core_cm7.h.
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
Definition at line 1215 of file core_cm7.h.
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
Definition at line 1218 of file core_cm7.h.
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
Definition at line 1219 of file core_cm7.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
Definition at line 1222 of file core_cm7.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
Definition at line 1223 of file core_cm7.h.
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
Definition at line 1226 of file core_cm7.h.
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
Definition at line 1227 of file core_cm7.h.
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
Definition at line 1230 of file core_cm7.h.
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
Definition at line 1231 of file core_cm7.h.
| #define DWT_MASK_MASK_Pos 0U |
DWT MASK: MASK Position
Definition at line 1234 of file core_cm7.h.
| #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) |
DWT MASK: MASK Mask
Definition at line 1235 of file core_cm7.h.
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
Definition at line 1238 of file core_cm7.h.
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
Definition at line 1239 of file core_cm7.h.
| #define DWT_FUNCTION_DATAVADDR1_Pos 16U |
DWT FUNCTION: DATAVADDR1 Position
Definition at line 1241 of file core_cm7.h.
| #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) |
DWT FUNCTION: DATAVADDR1 Mask
Definition at line 1242 of file core_cm7.h.
| #define DWT_FUNCTION_DATAVADDR0_Pos 12U |
DWT FUNCTION: DATAVADDR0 Position
Definition at line 1244 of file core_cm7.h.
| #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) |
DWT FUNCTION: DATAVADDR0 Mask
Definition at line 1245 of file core_cm7.h.
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
Definition at line 1247 of file core_cm7.h.
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
Definition at line 1248 of file core_cm7.h.
| #define DWT_FUNCTION_LNK1ENA_Pos 9U |
DWT FUNCTION: LNK1ENA Position
Definition at line 1250 of file core_cm7.h.
| #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) |
DWT FUNCTION: LNK1ENA Mask
Definition at line 1251 of file core_cm7.h.
| #define DWT_FUNCTION_DATAVMATCH_Pos 8U |
DWT FUNCTION: DATAVMATCH Position
Definition at line 1253 of file core_cm7.h.
| #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) |
DWT FUNCTION: DATAVMATCH Mask
Definition at line 1254 of file core_cm7.h.
| #define DWT_FUNCTION_CYCMATCH_Pos 7U |
DWT FUNCTION: CYCMATCH Position
Definition at line 1256 of file core_cm7.h.
| #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) |
DWT FUNCTION: CYCMATCH Mask
Definition at line 1257 of file core_cm7.h.
| #define DWT_FUNCTION_EMITRANGE_Pos 5U |
DWT FUNCTION: EMITRANGE Position
Definition at line 1259 of file core_cm7.h.
| #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) |
DWT FUNCTION: EMITRANGE Mask
Definition at line 1260 of file core_cm7.h.
| #define DWT_FUNCTION_FUNCTION_Pos 0U |
DWT FUNCTION: FUNCTION Position
Definition at line 1262 of file core_cm7.h.
| #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) |
DWT FUNCTION: FUNCTION Mask
Definition at line 1263 of file core_cm7.h.
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
Definition at line 1307 of file core_cm7.h.
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
Definition at line 1308 of file core_cm7.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 1311 of file core_cm7.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 1312 of file core_cm7.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 1315 of file core_cm7.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 1316 of file core_cm7.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 1318 of file core_cm7.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 1319 of file core_cm7.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 1321 of file core_cm7.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 1322 of file core_cm7.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 1324 of file core_cm7.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 1325 of file core_cm7.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 1328 of file core_cm7.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 1329 of file core_cm7.h.
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
Definition at line 1331 of file core_cm7.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 1332 of file core_cm7.h.
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
Definition at line 1335 of file core_cm7.h.
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
Definition at line 1336 of file core_cm7.h.
| #define TPI_FIFO0_ITM_ATVALID_Pos 29U |
TPI FIFO0: ITM_ATVALID Position
Definition at line 1339 of file core_cm7.h.
| #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
Definition at line 1340 of file core_cm7.h.
| #define TPI_FIFO0_ITM_bytecount_Pos 27U |
TPI FIFO0: ITM_bytecount Position
Definition at line 1342 of file core_cm7.h.
| #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
Definition at line 1343 of file core_cm7.h.
| #define TPI_FIFO0_ETM_ATVALID_Pos 26U |
TPI FIFO0: ETM_ATVALID Position
Definition at line 1345 of file core_cm7.h.
| #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
Definition at line 1346 of file core_cm7.h.
| #define TPI_FIFO0_ETM_bytecount_Pos 24U |
TPI FIFO0: ETM_bytecount Position
Definition at line 1348 of file core_cm7.h.
| #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
Definition at line 1349 of file core_cm7.h.
| #define TPI_FIFO0_ETM2_Pos 16U |
TPI FIFO0: ETM2 Position
Definition at line 1351 of file core_cm7.h.
| #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
Definition at line 1352 of file core_cm7.h.
| #define TPI_FIFO0_ETM1_Pos 8U |
TPI FIFO0: ETM1 Position
Definition at line 1354 of file core_cm7.h.
| #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
Definition at line 1355 of file core_cm7.h.
| #define TPI_FIFO0_ETM0_Pos 0U |
TPI FIFO0: ETM0 Position
Definition at line 1357 of file core_cm7.h.
| #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
TPI FIFO0: ETM0 Mask
Definition at line 1358 of file core_cm7.h.
| #define TPI_ITATBCTR2_ATREADY2_Pos 0U |
TPI ITATBCTR2: ATREADY2 Position
Definition at line 1361 of file core_cm7.h.
| #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) |
TPI ITATBCTR2: ATREADY2 Mask
Definition at line 1362 of file core_cm7.h.
| #define TPI_ITATBCTR2_ATREADY1_Pos 0U |
TPI ITATBCTR2: ATREADY1 Position
Definition at line 1364 of file core_cm7.h.
| #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) |
TPI ITATBCTR2: ATREADY1 Mask
Definition at line 1365 of file core_cm7.h.
| #define TPI_FIFO1_ITM_ATVALID_Pos 29U |
TPI FIFO1: ITM_ATVALID Position
Definition at line 1368 of file core_cm7.h.
| #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
Definition at line 1369 of file core_cm7.h.
| #define TPI_FIFO1_ITM_bytecount_Pos 27U |
TPI FIFO1: ITM_bytecount Position
Definition at line 1371 of file core_cm7.h.
| #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
Definition at line 1372 of file core_cm7.h.
| #define TPI_FIFO1_ETM_ATVALID_Pos 26U |
TPI FIFO1: ETM_ATVALID Position
Definition at line 1374 of file core_cm7.h.
| #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
Definition at line 1375 of file core_cm7.h.
| #define TPI_FIFO1_ETM_bytecount_Pos 24U |
TPI FIFO1: ETM_bytecount Position
Definition at line 1377 of file core_cm7.h.
| #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
Definition at line 1378 of file core_cm7.h.
| #define TPI_FIFO1_ITM2_Pos 16U |
TPI FIFO1: ITM2 Position
Definition at line 1380 of file core_cm7.h.
| #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
Definition at line 1381 of file core_cm7.h.
| #define TPI_FIFO1_ITM1_Pos 8U |
TPI FIFO1: ITM1 Position
Definition at line 1383 of file core_cm7.h.
| #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
Definition at line 1384 of file core_cm7.h.
| #define TPI_FIFO1_ITM0_Pos 0U |
TPI FIFO1: ITM0 Position
Definition at line 1386 of file core_cm7.h.
| #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
TPI FIFO1: ITM0 Mask
Definition at line 1387 of file core_cm7.h.
| #define TPI_ITATBCTR0_ATREADY2_Pos 0U |
TPI ITATBCTR0: ATREADY2 Position
Definition at line 1390 of file core_cm7.h.
| #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) |
TPI ITATBCTR0: ATREADY2 Mask
Definition at line 1391 of file core_cm7.h.
| #define TPI_ITATBCTR0_ATREADY1_Pos 0U |
TPI ITATBCTR0: ATREADY1 Position
Definition at line 1393 of file core_cm7.h.
| #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) |
TPI ITATBCTR0: ATREADY1 Mask
Definition at line 1394 of file core_cm7.h.
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
Definition at line 1397 of file core_cm7.h.
| #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
Definition at line 1398 of file core_cm7.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 1401 of file core_cm7.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1402 of file core_cm7.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 1404 of file core_cm7.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1405 of file core_cm7.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 1407 of file core_cm7.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1408 of file core_cm7.h.
| #define TPI_DEVID_MinBufSz_Pos 6U |
TPI DEVID: MinBufSz Position
Definition at line 1410 of file core_cm7.h.
| #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
Definition at line 1411 of file core_cm7.h.
| #define TPI_DEVID_AsynClkIn_Pos 5U |
TPI DEVID: AsynClkIn Position
Definition at line 1413 of file core_cm7.h.
| #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
Definition at line 1414 of file core_cm7.h.
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
Definition at line 1416 of file core_cm7.h.
| #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
Definition at line 1417 of file core_cm7.h.
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
Definition at line 1420 of file core_cm7.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 1421 of file core_cm7.h.
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
Definition at line 1423 of file core_cm7.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1424 of file core_cm7.h.
| #define MPU_TYPE_IREGION_Pos 16U |
MPU TYPE: IREGION Position
Definition at line 1458 of file core_cm7.h.
| #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) |
MPU TYPE: IREGION Mask
Definition at line 1459 of file core_cm7.h.
| #define MPU_TYPE_DREGION_Pos 8U |
MPU TYPE: DREGION Position
Definition at line 1461 of file core_cm7.h.
| #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) |
MPU TYPE: DREGION Mask
Definition at line 1462 of file core_cm7.h.
| #define MPU_TYPE_SEPARATE_Pos 0U |
MPU TYPE: SEPARATE Position
Definition at line 1464 of file core_cm7.h.
| #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) |
MPU TYPE: SEPARATE Mask
Definition at line 1465 of file core_cm7.h.
| #define MPU_CTRL_PRIVDEFENA_Pos 2U |
MPU CTRL: PRIVDEFENA Position
Definition at line 1468 of file core_cm7.h.
| #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) |
MPU CTRL: PRIVDEFENA Mask
Definition at line 1469 of file core_cm7.h.
| #define MPU_CTRL_HFNMIENA_Pos 1U |
MPU CTRL: HFNMIENA Position
Definition at line 1471 of file core_cm7.h.
| #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) |
MPU CTRL: HFNMIENA Mask
Definition at line 1472 of file core_cm7.h.
| #define MPU_CTRL_ENABLE_Pos 0U |
MPU CTRL: ENABLE Position
Definition at line 1474 of file core_cm7.h.
| #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) |
MPU CTRL: ENABLE Mask
Definition at line 1475 of file core_cm7.h.
| #define MPU_RNR_REGION_Pos 0U |
MPU RNR: REGION Position
Definition at line 1478 of file core_cm7.h.
| #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) |
MPU RNR: REGION Mask
Definition at line 1479 of file core_cm7.h.
| #define MPU_RBAR_ADDR_Pos 5U |
MPU RBAR: ADDR Position
Definition at line 1482 of file core_cm7.h.
| #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) |
MPU RBAR: ADDR Mask
Definition at line 1483 of file core_cm7.h.
| #define MPU_RBAR_VALID_Pos 4U |
MPU RBAR: VALID Position
Definition at line 1485 of file core_cm7.h.
| #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) |
MPU RBAR: VALID Mask
Definition at line 1486 of file core_cm7.h.
| #define MPU_RBAR_REGION_Pos 0U |
MPU RBAR: REGION Position
Definition at line 1488 of file core_cm7.h.
| #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) |
MPU RBAR: REGION Mask
Definition at line 1489 of file core_cm7.h.
| #define MPU_RASR_ATTRS_Pos 16U |
MPU RASR: MPU Region Attribute field Position
Definition at line 1492 of file core_cm7.h.
| #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) |
MPU RASR: MPU Region Attribute field Mask
Definition at line 1493 of file core_cm7.h.
| #define MPU_RASR_XN_Pos 28U |
MPU RASR: ATTRS.XN Position
Definition at line 1495 of file core_cm7.h.
| #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) |
MPU RASR: ATTRS.XN Mask
Definition at line 1496 of file core_cm7.h.
| #define MPU_RASR_AP_Pos 24U |
MPU RASR: ATTRS.AP Position
Definition at line 1498 of file core_cm7.h.
| #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) |
MPU RASR: ATTRS.AP Mask
Definition at line 1499 of file core_cm7.h.
| #define MPU_RASR_TEX_Pos 19U |
MPU RASR: ATTRS.TEX Position
Definition at line 1501 of file core_cm7.h.
| #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) |
MPU RASR: ATTRS.TEX Mask
Definition at line 1502 of file core_cm7.h.
| #define MPU_RASR_S_Pos 18U |
MPU RASR: ATTRS.S Position
Definition at line 1504 of file core_cm7.h.
| #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) |
MPU RASR: ATTRS.S Mask
Definition at line 1505 of file core_cm7.h.
| #define MPU_RASR_C_Pos 17U |
MPU RASR: ATTRS.C Position
Definition at line 1507 of file core_cm7.h.
| #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) |
MPU RASR: ATTRS.C Mask
Definition at line 1508 of file core_cm7.h.
| #define MPU_RASR_B_Pos 16U |
MPU RASR: ATTRS.B Position
Definition at line 1510 of file core_cm7.h.
| #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) |
MPU RASR: ATTRS.B Mask
Definition at line 1511 of file core_cm7.h.
| #define MPU_RASR_SRD_Pos 8U |
MPU RASR: Sub-Region Disable Position
Definition at line 1513 of file core_cm7.h.
| #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) |
MPU RASR: Sub-Region Disable Mask
Definition at line 1514 of file core_cm7.h.
| #define MPU_RASR_SIZE_Pos 1U |
MPU RASR: Region Size Field Position
Definition at line 1516 of file core_cm7.h.
| #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) |
MPU RASR: Region Size Field Mask
Definition at line 1517 of file core_cm7.h.
| #define MPU_RASR_ENABLE_Pos 0U |
MPU RASR: Region enable bit Position
Definition at line 1519 of file core_cm7.h.
| #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) |
MPU RASR: Region enable bit Disable Mask
Definition at line 1520 of file core_cm7.h.
| #define FPU_FPCCR_ASPEN_Pos 31U |
FPCCR: ASPEN bit Position
Definition at line 1548 of file core_cm7.h.
| #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) |
FPCCR: ASPEN bit Mask
Definition at line 1549 of file core_cm7.h.
| #define FPU_FPCCR_LSPEN_Pos 30U |
FPCCR: LSPEN Position
Definition at line 1551 of file core_cm7.h.
| #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) |
FPCCR: LSPEN bit Mask
Definition at line 1552 of file core_cm7.h.
| #define FPU_FPCCR_MONRDY_Pos 8U |
FPCCR: MONRDY Position
Definition at line 1554 of file core_cm7.h.
| #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) |
FPCCR: MONRDY bit Mask
Definition at line 1555 of file core_cm7.h.
| #define FPU_FPCCR_BFRDY_Pos 6U |
FPCCR: BFRDY Position
Definition at line 1557 of file core_cm7.h.
| #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) |
FPCCR: BFRDY bit Mask
Definition at line 1558 of file core_cm7.h.
| #define FPU_FPCCR_MMRDY_Pos 5U |
FPCCR: MMRDY Position
Definition at line 1560 of file core_cm7.h.
| #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) |
FPCCR: MMRDY bit Mask
Definition at line 1561 of file core_cm7.h.
| #define FPU_FPCCR_HFRDY_Pos 4U |
FPCCR: HFRDY Position
Definition at line 1563 of file core_cm7.h.
| #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) |
FPCCR: HFRDY bit Mask
Definition at line 1564 of file core_cm7.h.
| #define FPU_FPCCR_THREAD_Pos 3U |
FPCCR: processor mode bit Position
Definition at line 1566 of file core_cm7.h.
| #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) |
FPCCR: processor mode active bit Mask
Definition at line 1567 of file core_cm7.h.
| #define FPU_FPCCR_USER_Pos 1U |
FPCCR: privilege level bit Position
Definition at line 1569 of file core_cm7.h.
| #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) |
FPCCR: privilege level bit Mask
Definition at line 1570 of file core_cm7.h.
| #define FPU_FPCCR_LSPACT_Pos 0U |
FPCCR: Lazy state preservation active bit Position
Definition at line 1572 of file core_cm7.h.
| #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) |
FPCCR: Lazy state preservation active bit Mask
Definition at line 1573 of file core_cm7.h.
| #define FPU_FPCAR_ADDRESS_Pos 3U |
FPCAR: ADDRESS bit Position
Definition at line 1576 of file core_cm7.h.
| #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) |
FPCAR: ADDRESS bit Mask
Definition at line 1577 of file core_cm7.h.
| #define FPU_FPDSCR_AHP_Pos 26U |
FPDSCR: AHP bit Position
Definition at line 1580 of file core_cm7.h.
| #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) |
FPDSCR: AHP bit Mask
Definition at line 1581 of file core_cm7.h.
| #define FPU_FPDSCR_DN_Pos 25U |
FPDSCR: DN bit Position
Definition at line 1583 of file core_cm7.h.
| #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) |
FPDSCR: DN bit Mask
Definition at line 1584 of file core_cm7.h.
| #define FPU_FPDSCR_FZ_Pos 24U |
FPDSCR: FZ bit Position
Definition at line 1586 of file core_cm7.h.
| #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) |
FPDSCR: FZ bit Mask
Definition at line 1587 of file core_cm7.h.
| #define FPU_FPDSCR_RMode_Pos 22U |
FPDSCR: RMode bit Position
Definition at line 1589 of file core_cm7.h.
| #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) |
FPDSCR: RMode bit Mask
Definition at line 1590 of file core_cm7.h.
| #define FPU_MVFR0_FP_rounding_modes_Pos 28U |
MVFR0: FP rounding modes bits Position
Definition at line 1593 of file core_cm7.h.
| #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) |
MVFR0: FP rounding modes bits Mask
Definition at line 1594 of file core_cm7.h.
| #define FPU_MVFR0_Short_vectors_Pos 24U |
MVFR0: Short vectors bits Position
Definition at line 1596 of file core_cm7.h.
| #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) |
MVFR0: Short vectors bits Mask
Definition at line 1597 of file core_cm7.h.
| #define FPU_MVFR0_Square_root_Pos 20U |
MVFR0: Square root bits Position
Definition at line 1599 of file core_cm7.h.
| #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) |
MVFR0: Square root bits Mask
Definition at line 1600 of file core_cm7.h.
| #define FPU_MVFR0_Divide_Pos 16U |
MVFR0: Divide bits Position
Definition at line 1602 of file core_cm7.h.
| #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) |
MVFR0: Divide bits Mask
Definition at line 1603 of file core_cm7.h.
| #define FPU_MVFR0_FP_excep_trapping_Pos 12U |
MVFR0: FP exception trapping bits Position
Definition at line 1605 of file core_cm7.h.
| #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) |
MVFR0: FP exception trapping bits Mask
Definition at line 1606 of file core_cm7.h.
| #define FPU_MVFR0_Double_precision_Pos 8U |
MVFR0: Double-precision bits Position
Definition at line 1608 of file core_cm7.h.
| #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) |
MVFR0: Double-precision bits Mask
Definition at line 1609 of file core_cm7.h.
| #define FPU_MVFR0_Single_precision_Pos 4U |
MVFR0: Single-precision bits Position
Definition at line 1611 of file core_cm7.h.
| #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) |
MVFR0: Single-precision bits Mask
Definition at line 1612 of file core_cm7.h.
| #define FPU_MVFR0_A_SIMD_registers_Pos 0U |
MVFR0: A_SIMD registers bits Position
Definition at line 1614 of file core_cm7.h.
| #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) |
MVFR0: A_SIMD registers bits Mask
Definition at line 1615 of file core_cm7.h.
| #define FPU_MVFR1_FP_fused_MAC_Pos 28U |
MVFR1: FP fused MAC bits Position
Definition at line 1618 of file core_cm7.h.
| #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) |
MVFR1: FP fused MAC bits Mask
Definition at line 1619 of file core_cm7.h.
| #define FPU_MVFR1_FP_HPFP_Pos 24U |
MVFR1: FP HPFP bits Position
Definition at line 1621 of file core_cm7.h.
| #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) |
MVFR1: FP HPFP bits Mask
Definition at line 1622 of file core_cm7.h.
| #define FPU_MVFR1_D_NaN_mode_Pos 4U |
MVFR1: D_NaN mode bits Position
Definition at line 1624 of file core_cm7.h.
| #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) |
MVFR1: D_NaN mode bits Mask
Definition at line 1625 of file core_cm7.h.
| #define FPU_MVFR1_FtZ_mode_Pos 0U |
MVFR1: FtZ mode bits Position
Definition at line 1627 of file core_cm7.h.
| #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) |
MVFR1: FtZ mode bits Mask
Definition at line 1628 of file core_cm7.h.
| #define CoreDebug_DHCSR_DBGKEY_Pos 16U |
CoreDebug DHCSR: DBGKEY Position
Definition at line 1657 of file core_cm7.h.
| #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
CoreDebug DHCSR: DBGKEY Mask
Definition at line 1658 of file core_cm7.h.
| #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
CoreDebug DHCSR: S_RESET_ST Position
Definition at line 1660 of file core_cm7.h.
| #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
CoreDebug DHCSR: S_RESET_ST Mask
Definition at line 1661 of file core_cm7.h.
| #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
CoreDebug DHCSR: S_RETIRE_ST Position
Definition at line 1663 of file core_cm7.h.
| #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
CoreDebug DHCSR: S_RETIRE_ST Mask
Definition at line 1664 of file core_cm7.h.
| #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
CoreDebug DHCSR: S_LOCKUP Position
Definition at line 1666 of file core_cm7.h.
| #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
CoreDebug DHCSR: S_LOCKUP Mask
Definition at line 1667 of file core_cm7.h.
| #define CoreDebug_DHCSR_S_SLEEP_Pos 18U |
CoreDebug DHCSR: S_SLEEP Position
Definition at line 1669 of file core_cm7.h.
| #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
CoreDebug DHCSR: S_SLEEP Mask
Definition at line 1670 of file core_cm7.h.
| #define CoreDebug_DHCSR_S_HALT_Pos 17U |
CoreDebug DHCSR: S_HALT Position
Definition at line 1672 of file core_cm7.h.
| #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
CoreDebug DHCSR: S_HALT Mask
Definition at line 1673 of file core_cm7.h.
| #define CoreDebug_DHCSR_S_REGRDY_Pos 16U |
CoreDebug DHCSR: S_REGRDY Position
Definition at line 1675 of file core_cm7.h.
| #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
CoreDebug DHCSR: S_REGRDY Mask
Definition at line 1676 of file core_cm7.h.
| #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U |
CoreDebug DHCSR: C_SNAPSTALL Position
Definition at line 1678 of file core_cm7.h.
| #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) |
CoreDebug DHCSR: C_SNAPSTALL Mask
Definition at line 1679 of file core_cm7.h.
| #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
CoreDebug DHCSR: C_MASKINTS Position
Definition at line 1681 of file core_cm7.h.
| #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
CoreDebug DHCSR: C_MASKINTS Mask
Definition at line 1682 of file core_cm7.h.
| #define CoreDebug_DHCSR_C_STEP_Pos 2U |
CoreDebug DHCSR: C_STEP Position
Definition at line 1684 of file core_cm7.h.
| #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
CoreDebug DHCSR: C_STEP Mask
Definition at line 1685 of file core_cm7.h.
| #define CoreDebug_DHCSR_C_HALT_Pos 1U |
CoreDebug DHCSR: C_HALT Position
Definition at line 1687 of file core_cm7.h.
| #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
CoreDebug DHCSR: C_HALT Mask
Definition at line 1688 of file core_cm7.h.
| #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
CoreDebug DHCSR: C_DEBUGEN Position
Definition at line 1690 of file core_cm7.h.
| #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
CoreDebug DHCSR: C_DEBUGEN Mask
Definition at line 1691 of file core_cm7.h.
| #define CoreDebug_DCRSR_REGWnR_Pos 16U |
CoreDebug DCRSR: REGWnR Position
Definition at line 1694 of file core_cm7.h.
| #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
CoreDebug DCRSR: REGWnR Mask
Definition at line 1695 of file core_cm7.h.
| #define CoreDebug_DCRSR_REGSEL_Pos 0U |
CoreDebug DCRSR: REGSEL Position
Definition at line 1697 of file core_cm7.h.
| #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
CoreDebug DCRSR: REGSEL Mask
Definition at line 1698 of file core_cm7.h.
| #define CoreDebug_DEMCR_TRCENA_Pos 24U |
CoreDebug DEMCR: TRCENA Position
Definition at line 1701 of file core_cm7.h.
| #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) |
CoreDebug DEMCR: TRCENA Mask
Definition at line 1702 of file core_cm7.h.
| #define CoreDebug_DEMCR_MON_REQ_Pos 19U |
CoreDebug DEMCR: MON_REQ Position
Definition at line 1704 of file core_cm7.h.
| #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) |
CoreDebug DEMCR: MON_REQ Mask
Definition at line 1705 of file core_cm7.h.
| #define CoreDebug_DEMCR_MON_STEP_Pos 18U |
CoreDebug DEMCR: MON_STEP Position
Definition at line 1707 of file core_cm7.h.
| #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) |
CoreDebug DEMCR: MON_STEP Mask
Definition at line 1708 of file core_cm7.h.
| #define CoreDebug_DEMCR_MON_PEND_Pos 17U |
CoreDebug DEMCR: MON_PEND Position
Definition at line 1710 of file core_cm7.h.
| #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) |
CoreDebug DEMCR: MON_PEND Mask
Definition at line 1711 of file core_cm7.h.
| #define CoreDebug_DEMCR_MON_EN_Pos 16U |
CoreDebug DEMCR: MON_EN Position
Definition at line 1713 of file core_cm7.h.
| #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) |
CoreDebug DEMCR: MON_EN Mask
Definition at line 1714 of file core_cm7.h.
| #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
CoreDebug DEMCR: VC_HARDERR Position
Definition at line 1716 of file core_cm7.h.
| #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
CoreDebug DEMCR: VC_HARDERR Mask
Definition at line 1717 of file core_cm7.h.
| #define CoreDebug_DEMCR_VC_INTERR_Pos 9U |
CoreDebug DEMCR: VC_INTERR Position
Definition at line 1719 of file core_cm7.h.
| #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) |
CoreDebug DEMCR: VC_INTERR Mask
Definition at line 1720 of file core_cm7.h.
| #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U |
CoreDebug DEMCR: VC_BUSERR Position
Definition at line 1722 of file core_cm7.h.
| #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) |
CoreDebug DEMCR: VC_BUSERR Mask
Definition at line 1723 of file core_cm7.h.
| #define CoreDebug_DEMCR_VC_STATERR_Pos 7U |
CoreDebug DEMCR: VC_STATERR Position
Definition at line 1725 of file core_cm7.h.
| #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) |
CoreDebug DEMCR: VC_STATERR Mask
Definition at line 1726 of file core_cm7.h.
| #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U |
CoreDebug DEMCR: VC_CHKERR Position
Definition at line 1728 of file core_cm7.h.
| #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) |
CoreDebug DEMCR: VC_CHKERR Mask
Definition at line 1729 of file core_cm7.h.
| #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U |
CoreDebug DEMCR: VC_NOCPERR Position
Definition at line 1731 of file core_cm7.h.
| #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) |
CoreDebug DEMCR: VC_NOCPERR Mask
Definition at line 1732 of file core_cm7.h.
| #define CoreDebug_DEMCR_VC_MMERR_Pos 4U |
CoreDebug DEMCR: VC_MMERR Position
Definition at line 1734 of file core_cm7.h.
| #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) |
CoreDebug DEMCR: VC_MMERR Mask
Definition at line 1735 of file core_cm7.h.
| #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
CoreDebug DEMCR: VC_CORERESET Position
Definition at line 1737 of file core_cm7.h.
| #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
CoreDebug DEMCR: VC_CORERESET Mask
Definition at line 1738 of file core_cm7.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 1756 of file core_cm7.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 1764 of file core_cm7.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 1777 of file core_cm7.h.
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
Definition at line 1778 of file core_cm7.h.
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
Definition at line 1779 of file core_cm7.h.
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
Definition at line 1780 of file core_cm7.h.
| #define CoreDebug_BASE (0xE000EDF0UL) |
Core Debug Base Address
Definition at line 1781 of file core_cm7.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 1782 of file core_cm7.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 1783 of file core_cm7.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 1784 of file core_cm7.h.
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
Definition at line 1786 of file core_cm7.h.
SCB configuration struct
Definition at line 1787 of file core_cm7.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 1788 of file core_cm7.h.
NVIC configuration struct
Definition at line 1789 of file core_cm7.h.
ITM configuration struct
Definition at line 1790 of file core_cm7.h.
DWT configuration struct
Definition at line 1791 of file core_cm7.h.
TPI configuration struct
Definition at line 1792 of file core_cm7.h.
| #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) |
Core Debug configuration struct
Definition at line 1793 of file core_cm7.h.
| #define MPU_BASE (SCS_BASE + 0x0D90UL) |
Memory Protection Unit
Definition at line 1796 of file core_cm7.h.
Memory Protection Unit
Definition at line 1797 of file core_cm7.h.
| #define FPU_BASE (SCS_BASE + 0x0F30UL) |
Floating Point Unit
Definition at line 1800 of file core_cm7.h.
Floating Point Unit
Definition at line 1801 of file core_cm7.h.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 2290 of file core_cm7.h.
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
Definition at line 514 of file core_cm85.h.
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
Definition at line 515 of file core_cm85.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 582 of file core_cm85.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 583 of file core_cm85.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 585 of file core_cm85.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 586 of file core_cm85.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 588 of file core_cm85.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 589 of file core_cm85.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 591 of file core_cm85.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 592 of file core_cm85.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 594 of file core_cm85.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 595 of file core_cm85.h.
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
Definition at line 598 of file core_cm85.h.
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
Definition at line 599 of file core_cm85.h.
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
Definition at line 601 of file core_cm85.h.
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
Definition at line 602 of file core_cm85.h.
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
Definition at line 604 of file core_cm85.h.
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
Definition at line 605 of file core_cm85.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 607 of file core_cm85.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 608 of file core_cm85.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 610 of file core_cm85.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 611 of file core_cm85.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 613 of file core_cm85.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 614 of file core_cm85.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 616 of file core_cm85.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 617 of file core_cm85.h.
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
Definition at line 619 of file core_cm85.h.
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
Definition at line 620 of file core_cm85.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 622 of file core_cm85.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 623 of file core_cm85.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 625 of file core_cm85.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 626 of file core_cm85.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 628 of file core_cm85.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 629 of file core_cm85.h.
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
Definition at line 631 of file core_cm85.h.
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
Definition at line 632 of file core_cm85.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 634 of file core_cm85.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 635 of file core_cm85.h.
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
Definition at line 638 of file core_cm85.h.
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
Definition at line 639 of file core_cm85.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 642 of file core_cm85.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 643 of file core_cm85.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 645 of file core_cm85.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 646 of file core_cm85.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 648 of file core_cm85.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 649 of file core_cm85.h.
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
Definition at line 651 of file core_cm85.h.
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
Definition at line 652 of file core_cm85.h.
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
Definition at line 654 of file core_cm85.h.
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
Definition at line 655 of file core_cm85.h.
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
Definition at line 657 of file core_cm85.h.
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
Definition at line 658 of file core_cm85.h.
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
Definition at line 666 of file core_cm85.h.
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
Definition at line 667 of file core_cm85.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 669 of file core_cm85.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 670 of file core_cm85.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 672 of file core_cm85.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 673 of file core_cm85.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 676 of file core_cm85.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 677 of file core_cm85.h.
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
Definition at line 679 of file core_cm85.h.
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
Definition at line 680 of file core_cm85.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 682 of file core_cm85.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 683 of file core_cm85.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 685 of file core_cm85.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 686 of file core_cm85.h.
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
Definition at line 695 of file core_cm85.h.
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
Definition at line 696 of file core_cm85.h.
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
Definition at line 698 of file core_cm85.h.
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
Definition at line 699 of file core_cm85.h.
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
Definition at line 701 of file core_cm85.h.
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
SCB CCR: DC Mask
Definition at line 702 of file core_cm85.h.
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
Definition at line 704 of file core_cm85.h.
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
Definition at line 705 of file core_cm85.h.
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
Definition at line 707 of file core_cm85.h.
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
Definition at line 708 of file core_cm85.h.
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
Definition at line 710 of file core_cm85.h.
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
Definition at line 711 of file core_cm85.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 713 of file core_cm85.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 714 of file core_cm85.h.
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
Definition at line 716 of file core_cm85.h.
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
Definition at line 717 of file core_cm85.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
Definition at line 720 of file core_cm85.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
Definition at line 721 of file core_cm85.h.
| #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
SCB SHCSR: SECUREFAULTPENDED Position
Definition at line 723 of file core_cm85.h.
| #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
SCB SHCSR: SECUREFAULTPENDED Mask
Definition at line 724 of file core_cm85.h.
| #define SCB_SHCSR_SECUREFAULTENA_Pos 19U |
SCB SHCSR: SECUREFAULTENA Position
Definition at line 726 of file core_cm85.h.
| #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
SCB SHCSR: SECUREFAULTENA Mask
Definition at line 727 of file core_cm85.h.
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
Definition at line 729 of file core_cm85.h.
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
Definition at line 730 of file core_cm85.h.
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
Definition at line 732 of file core_cm85.h.
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
Definition at line 733 of file core_cm85.h.
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
Definition at line 735 of file core_cm85.h.
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
Definition at line 736 of file core_cm85.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 738 of file core_cm85.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 739 of file core_cm85.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
Definition at line 741 of file core_cm85.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
Definition at line 742 of file core_cm85.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
Definition at line 744 of file core_cm85.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
Definition at line 745 of file core_cm85.h.
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
Definition at line 747 of file core_cm85.h.
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
Definition at line 748 of file core_cm85.h.
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
Definition at line 750 of file core_cm85.h.
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
Definition at line 751 of file core_cm85.h.
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
Definition at line 753 of file core_cm85.h.
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
Definition at line 754 of file core_cm85.h.
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
Definition at line 756 of file core_cm85.h.
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
Definition at line 757 of file core_cm85.h.
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
Definition at line 759 of file core_cm85.h.
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
Definition at line 760 of file core_cm85.h.
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
Definition at line 762 of file core_cm85.h.
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
Definition at line 763 of file core_cm85.h.
| #define SCB_SHCSR_SECUREFAULTACT_Pos 4U |
SCB SHCSR: SECUREFAULTACT Position
Definition at line 765 of file core_cm85.h.
| #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
SCB SHCSR: SECUREFAULTACT Mask
Definition at line 766 of file core_cm85.h.
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
Definition at line 768 of file core_cm85.h.
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
Definition at line 769 of file core_cm85.h.
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
Definition at line 771 of file core_cm85.h.
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
Definition at line 772 of file core_cm85.h.
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
Definition at line 774 of file core_cm85.h.
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
Definition at line 775 of file core_cm85.h.
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
Definition at line 777 of file core_cm85.h.
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
Definition at line 778 of file core_cm85.h.
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
Definition at line 781 of file core_cm85.h.
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
Definition at line 782 of file core_cm85.h.
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
Definition at line 784 of file core_cm85.h.
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
Definition at line 785 of file core_cm85.h.
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
Definition at line 787 of file core_cm85.h.
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
Definition at line 788 of file core_cm85.h.
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
Definition at line 791 of file core_cm85.h.
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
Definition at line 792 of file core_cm85.h.
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
Definition at line 794 of file core_cm85.h.
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
Definition at line 795 of file core_cm85.h.
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
Definition at line 797 of file core_cm85.h.
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
Definition at line 798 of file core_cm85.h.
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
Definition at line 800 of file core_cm85.h.
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
Definition at line 801 of file core_cm85.h.
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
Definition at line 803 of file core_cm85.h.
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
Definition at line 804 of file core_cm85.h.
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
Definition at line 806 of file core_cm85.h.
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
Definition at line 807 of file core_cm85.h.
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
Definition at line 810 of file core_cm85.h.
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
Definition at line 811 of file core_cm85.h.
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
Definition at line 813 of file core_cm85.h.
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
Definition at line 814 of file core_cm85.h.
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
Definition at line 816 of file core_cm85.h.
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
Definition at line 817 of file core_cm85.h.
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
Definition at line 819 of file core_cm85.h.
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
Definition at line 820 of file core_cm85.h.
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
Definition at line 822 of file core_cm85.h.
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
Definition at line 823 of file core_cm85.h.
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
Definition at line 825 of file core_cm85.h.
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
Definition at line 826 of file core_cm85.h.
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
Definition at line 828 of file core_cm85.h.
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
Definition at line 829 of file core_cm85.h.
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
Definition at line 832 of file core_cm85.h.
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
Definition at line 833 of file core_cm85.h.
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
Definition at line 835 of file core_cm85.h.
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
Definition at line 836 of file core_cm85.h.
| #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
SCB CFSR (UFSR): STKOF Position
Definition at line 838 of file core_cm85.h.
| #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
SCB CFSR (UFSR): STKOF Mask
Definition at line 839 of file core_cm85.h.
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
Definition at line 841 of file core_cm85.h.
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
Definition at line 842 of file core_cm85.h.
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
Definition at line 844 of file core_cm85.h.
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
Definition at line 845 of file core_cm85.h.
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
Definition at line 847 of file core_cm85.h.
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
Definition at line 848 of file core_cm85.h.
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
Definition at line 850 of file core_cm85.h.
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
Definition at line 851 of file core_cm85.h.
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
Definition at line 854 of file core_cm85.h.
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
Definition at line 855 of file core_cm85.h.
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
Definition at line 857 of file core_cm85.h.
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
Definition at line 858 of file core_cm85.h.
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
Definition at line 860 of file core_cm85.h.
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
Definition at line 861 of file core_cm85.h.
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
Definition at line 867 of file core_cm85.h.
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
Definition at line 868 of file core_cm85.h.
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
Definition at line 870 of file core_cm85.h.
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
Definition at line 871 of file core_cm85.h.
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
Definition at line 873 of file core_cm85.h.
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
Definition at line 874 of file core_cm85.h.
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
Definition at line 876 of file core_cm85.h.
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
Definition at line 877 of file core_cm85.h.
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
Definition at line 879 of file core_cm85.h.
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
Definition at line 880 of file core_cm85.h.
| #define SCB_NSACR_CP11_Pos 11U |
SCB NSACR: CP11 Position
Definition at line 883 of file core_cm85.h.
| #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
SCB NSACR: CP11 Mask
Definition at line 884 of file core_cm85.h.
| #define SCB_NSACR_CP10_Pos 10U |
SCB NSACR: CP10 Position
Definition at line 886 of file core_cm85.h.
| #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
SCB NSACR: CP10 Mask
Definition at line 887 of file core_cm85.h.
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
Definition at line 921 of file core_cm85.h.
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
Definition at line 922 of file core_cm85.h.
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
Definition at line 924 of file core_cm85.h.
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
Definition at line 925 of file core_cm85.h.
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
Definition at line 928 of file core_cm85.h.
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
Definition at line 929 of file core_cm85.h.
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
Definition at line 931 of file core_cm85.h.
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
Definition at line 932 of file core_cm85.h.
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
Definition at line 934 of file core_cm85.h.
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
Definition at line 935 of file core_cm85.h.
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
Definition at line 937 of file core_cm85.h.
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
Definition at line 938 of file core_cm85.h.
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
Definition at line 940 of file core_cm85.h.
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
Definition at line 941 of file core_cm85.h.
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
Definition at line 944 of file core_cm85.h.
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
Definition at line 945 of file core_cm85.h.
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
Definition at line 947 of file core_cm85.h.
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
Definition at line 948 of file core_cm85.h.
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
Definition at line 950 of file core_cm85.h.
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
Definition at line 951 of file core_cm85.h.
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
Definition at line 953 of file core_cm85.h.
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
Definition at line 954 of file core_cm85.h.
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
Definition at line 956 of file core_cm85.h.
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
Definition at line 957 of file core_cm85.h.
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
Definition at line 959 of file core_cm85.h.
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
Definition at line 960 of file core_cm85.h.
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
Definition at line 962 of file core_cm85.h.
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
Definition at line 963 of file core_cm85.h.
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
Definition at line 966 of file core_cm85.h.
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
Definition at line 967 of file core_cm85.h.
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
Definition at line 969 of file core_cm85.h.
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
Definition at line 970 of file core_cm85.h.
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
Definition at line 973 of file core_cm85.h.
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
Definition at line 974 of file core_cm85.h.
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
Definition at line 987 of file core_cm85.h.
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
Definition at line 988 of file core_cm85.h.
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
Definition at line 990 of file core_cm85.h.
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
Definition at line 991 of file core_cm85.h.
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
Definition at line 994 of file core_cm85.h.
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
Definition at line 995 of file core_cm85.h.
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
Definition at line 997 of file core_cm85.h.
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
Definition at line 998 of file core_cm85.h.
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
Definition at line 1001 of file core_cm85.h.
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
Definition at line 1002 of file core_cm85.h.
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
Definition at line 1004 of file core_cm85.h.
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
Definition at line 1005 of file core_cm85.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 1076 of file core_cm85.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 1077 of file core_cm85.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 1079 of file core_cm85.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 1080 of file core_cm85.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 1082 of file core_cm85.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 1083 of file core_cm85.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 1085 of file core_cm85.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 1086 of file core_cm85.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 1089 of file core_cm85.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 1090 of file core_cm85.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 1093 of file core_cm85.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 1094 of file core_cm85.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 1097 of file core_cm85.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 1098 of file core_cm85.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 1100 of file core_cm85.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 1101 of file core_cm85.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 1103 of file core_cm85.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 1104 of file core_cm85.h.
| #define ITM_STIM_DISABLED_Pos 1U |
ITM STIM: DISABLED Position
Definition at line 1156 of file core_cm85.h.
| #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) |
ITM STIM: DISABLED Mask
Definition at line 1157 of file core_cm85.h.
| #define ITM_STIM_FIFOREADY_Pos 0U |
ITM STIM: FIFOREADY Position
Definition at line 1159 of file core_cm85.h.
| #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) |
ITM STIM: FIFOREADY Mask
Definition at line 1160 of file core_cm85.h.
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
Definition at line 1163 of file core_cm85.h.
| #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
Definition at line 1164 of file core_cm85.h.
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
Definition at line 1167 of file core_cm85.h.
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
Definition at line 1168 of file core_cm85.h.
| #define ITM_TCR_TRACEBUSID_Pos 16U |
ITM TCR: ATBID Position
Definition at line 1170 of file core_cm85.h.
| #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) |
ITM TCR: ATBID Mask
Definition at line 1171 of file core_cm85.h.
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
Definition at line 1173 of file core_cm85.h.
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
Definition at line 1174 of file core_cm85.h.
| #define ITM_TCR_TSPRESCALE_Pos 8U |
ITM TCR: TSPRESCALE Position
Definition at line 1176 of file core_cm85.h.
| #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) |
ITM TCR: TSPRESCALE Mask
Definition at line 1177 of file core_cm85.h.
| #define ITM_TCR_STALLENA_Pos 5U |
ITM TCR: STALLENA Position
Definition at line 1179 of file core_cm85.h.
| #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) |
ITM TCR: STALLENA Mask
Definition at line 1180 of file core_cm85.h.
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
Definition at line 1182 of file core_cm85.h.
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
Definition at line 1183 of file core_cm85.h.
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
Definition at line 1185 of file core_cm85.h.
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
Definition at line 1186 of file core_cm85.h.
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
Definition at line 1188 of file core_cm85.h.
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
Definition at line 1189 of file core_cm85.h.
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
Definition at line 1191 of file core_cm85.h.
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
Definition at line 1192 of file core_cm85.h.
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
Definition at line 1194 of file core_cm85.h.
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
Definition at line 1195 of file core_cm85.h.
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
Definition at line 1198 of file core_cm85.h.
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
Definition at line 1199 of file core_cm85.h.
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
Definition at line 1201 of file core_cm85.h.
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
Definition at line 1202 of file core_cm85.h.
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
Definition at line 1204 of file core_cm85.h.
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
Definition at line 1205 of file core_cm85.h.
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
Definition at line 1300 of file core_cm85.h.
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
Definition at line 1301 of file core_cm85.h.
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
Definition at line 1303 of file core_cm85.h.
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
Definition at line 1304 of file core_cm85.h.
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
Definition at line 1306 of file core_cm85.h.
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
Definition at line 1307 of file core_cm85.h.
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
Definition at line 1309 of file core_cm85.h.
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
Definition at line 1310 of file core_cm85.h.
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
Definition at line 1312 of file core_cm85.h.
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
Definition at line 1313 of file core_cm85.h.
| #define DWT_CTRL_CYCDISS_Pos 23U |
DWT CTRL: CYCDISS Position
Definition at line 1315 of file core_cm85.h.
| #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) |
DWT CTRL: CYCDISS Mask
Definition at line 1316 of file core_cm85.h.
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
Definition at line 1318 of file core_cm85.h.
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
Definition at line 1319 of file core_cm85.h.
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
Definition at line 1321 of file core_cm85.h.
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
Definition at line 1322 of file core_cm85.h.
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
Definition at line 1324 of file core_cm85.h.
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
Definition at line 1325 of file core_cm85.h.
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
Definition at line 1327 of file core_cm85.h.
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
Definition at line 1328 of file core_cm85.h.
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
Definition at line 1330 of file core_cm85.h.
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
Definition at line 1331 of file core_cm85.h.
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
Definition at line 1333 of file core_cm85.h.
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
Definition at line 1334 of file core_cm85.h.
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
Definition at line 1336 of file core_cm85.h.
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
Definition at line 1337 of file core_cm85.h.
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
Definition at line 1339 of file core_cm85.h.
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
Definition at line 1340 of file core_cm85.h.
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
Definition at line 1342 of file core_cm85.h.
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
Definition at line 1343 of file core_cm85.h.
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
Definition at line 1345 of file core_cm85.h.
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
Definition at line 1346 of file core_cm85.h.
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
Definition at line 1348 of file core_cm85.h.
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
Definition at line 1349 of file core_cm85.h.
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
Definition at line 1351 of file core_cm85.h.
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
Definition at line 1352 of file core_cm85.h.
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
Definition at line 1354 of file core_cm85.h.
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
Definition at line 1355 of file core_cm85.h.
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
Definition at line 1358 of file core_cm85.h.
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
Definition at line 1359 of file core_cm85.h.
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
Definition at line 1362 of file core_cm85.h.
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
Definition at line 1363 of file core_cm85.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
Definition at line 1366 of file core_cm85.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
Definition at line 1367 of file core_cm85.h.
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
Definition at line 1370 of file core_cm85.h.
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
Definition at line 1371 of file core_cm85.h.
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
Definition at line 1374 of file core_cm85.h.
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
Definition at line 1375 of file core_cm85.h.
| #define DWT_FUNCTION_ID_Pos 27U |
DWT FUNCTION: ID Position
Definition at line 1378 of file core_cm85.h.
| #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) |
DWT FUNCTION: ID Mask
Definition at line 1379 of file core_cm85.h.
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
Definition at line 1381 of file core_cm85.h.
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
Definition at line 1382 of file core_cm85.h.
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
Definition at line 1384 of file core_cm85.h.
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
Definition at line 1385 of file core_cm85.h.
| #define DWT_FUNCTION_ACTION_Pos 4U |
DWT FUNCTION: ACTION Position
Definition at line 1387 of file core_cm85.h.
| #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) |
DWT FUNCTION: ACTION Mask
Definition at line 1388 of file core_cm85.h.
| #define DWT_FUNCTION_MATCH_Pos 0U |
DWT FUNCTION: MATCH Position
Definition at line 1390 of file core_cm85.h.
| #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) |
DWT FUNCTION: MATCH Mask
Definition at line 1391 of file core_cm85.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 1790 of file core_cm85.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 1791 of file core_cm85.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 1794 of file core_cm85.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 1795 of file core_cm85.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 1797 of file core_cm85.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 1798 of file core_cm85.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 1800 of file core_cm85.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 1801 of file core_cm85.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 1803 of file core_cm85.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 1804 of file core_cm85.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 1807 of file core_cm85.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 1808 of file core_cm85.h.
| #define TPI_FFCR_FOnMan_Pos 6U |
TPI FFCR: FOnMan Position
Definition at line 1810 of file core_cm85.h.
| #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) |
TPI FFCR: FOnMan Mask
Definition at line 1811 of file core_cm85.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 1831 of file core_cm85.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1832 of file core_cm85.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 1834 of file core_cm85.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1835 of file core_cm85.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 1837 of file core_cm85.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1838 of file core_cm85.h.
| #define TPI_DEVID_FIFOSZ_Pos 6U |
TPI DEVID: FIFO depth Position
TPI DEVID: FIFOSZ Position
Definition at line 1840 of file core_cm85.h.
| #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) |
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
Definition at line 1844 of file core_cm85.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 1845 of file core_cm85.h.
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
Definition at line 1847 of file core_cm85.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1848 of file core_cm85.h.
| #define MPU_TYPE_IREGION_Pos 16U |
MPU TYPE: IREGION Position
Definition at line 2707 of file core_cm85.h.
| #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) |
MPU TYPE: IREGION Mask
Definition at line 2708 of file core_cm85.h.
| #define MPU_TYPE_DREGION_Pos 8U |
MPU TYPE: DREGION Position
Definition at line 2710 of file core_cm85.h.
| #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) |
MPU TYPE: DREGION Mask
Definition at line 2711 of file core_cm85.h.
| #define MPU_TYPE_SEPARATE_Pos 0U |
MPU TYPE: SEPARATE Position
Definition at line 2713 of file core_cm85.h.
| #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) |
MPU TYPE: SEPARATE Mask
Definition at line 2714 of file core_cm85.h.
| #define MPU_CTRL_PRIVDEFENA_Pos 2U |
MPU CTRL: PRIVDEFENA Position
Definition at line 2717 of file core_cm85.h.
| #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) |
MPU CTRL: PRIVDEFENA Mask
Definition at line 2718 of file core_cm85.h.
| #define MPU_CTRL_HFNMIENA_Pos 1U |
MPU CTRL: HFNMIENA Position
Definition at line 2720 of file core_cm85.h.
| #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) |
MPU CTRL: HFNMIENA Mask
Definition at line 2721 of file core_cm85.h.
| #define MPU_CTRL_ENABLE_Pos 0U |
MPU CTRL: ENABLE Position
Definition at line 2723 of file core_cm85.h.
| #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) |
MPU CTRL: ENABLE Mask
Definition at line 2724 of file core_cm85.h.
| #define MPU_RNR_REGION_Pos 0U |
MPU RNR: REGION Position
Definition at line 2727 of file core_cm85.h.
| #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) |
MPU RNR: REGION Mask
Definition at line 2728 of file core_cm85.h.
| #define MPU_RBAR_BASE_Pos 5U |
MPU RBAR: BASE Position
Definition at line 2731 of file core_cm85.h.
| #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) |
MPU RBAR: BASE Mask
Definition at line 2732 of file core_cm85.h.
| #define MPU_RBAR_SH_Pos 3U |
MPU RBAR: SH Position
Definition at line 2734 of file core_cm85.h.
| #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) |
MPU RBAR: SH Mask
Definition at line 2735 of file core_cm85.h.
| #define MPU_RBAR_AP_Pos 1U |
MPU RBAR: AP Position
Definition at line 2737 of file core_cm85.h.
| #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) |
MPU RBAR: AP Mask
Definition at line 2738 of file core_cm85.h.
| #define MPU_RBAR_XN_Pos 0U |
MPU RBAR: XN Position
Definition at line 2740 of file core_cm85.h.
| #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) |
MPU RBAR: XN Mask
Definition at line 2741 of file core_cm85.h.
| #define MPU_RLAR_LIMIT_Pos 5U |
MPU RLAR: LIMIT Position
Definition at line 2744 of file core_cm85.h.
| #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) |
MPU RLAR: LIMIT Mask
Definition at line 2745 of file core_cm85.h.
| #define MPU_RLAR_AttrIndx_Pos 1U |
MPU RLAR: AttrIndx Position
Definition at line 2750 of file core_cm85.h.
| #define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) |
MPU RLAR: AttrIndx Mask
Definition at line 2751 of file core_cm85.h.
| #define MPU_RLAR_EN_Pos 0U |
MPU RLAR: Region enable bit Position
Definition at line 2753 of file core_cm85.h.
| #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) |
MPU RLAR: Region enable bit Disable Mask
Definition at line 2754 of file core_cm85.h.
| #define MPU_MAIR0_Attr3_Pos 24U |
MPU MAIR0: Attr3 Position
Definition at line 2757 of file core_cm85.h.
| #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) |
MPU MAIR0: Attr3 Mask
Definition at line 2758 of file core_cm85.h.
| #define MPU_MAIR0_Attr2_Pos 16U |
MPU MAIR0: Attr2 Position
Definition at line 2760 of file core_cm85.h.
| #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) |
MPU MAIR0: Attr2 Mask
Definition at line 2761 of file core_cm85.h.
| #define MPU_MAIR0_Attr1_Pos 8U |
MPU MAIR0: Attr1 Position
Definition at line 2763 of file core_cm85.h.
| #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) |
MPU MAIR0: Attr1 Mask
Definition at line 2764 of file core_cm85.h.
| #define MPU_MAIR0_Attr0_Pos 0U |
MPU MAIR0: Attr0 Position
Definition at line 2766 of file core_cm85.h.
| #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) |
MPU MAIR0: Attr0 Mask
Definition at line 2767 of file core_cm85.h.
| #define MPU_MAIR1_Attr7_Pos 24U |
MPU MAIR1: Attr7 Position
Definition at line 2770 of file core_cm85.h.
| #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) |
MPU MAIR1: Attr7 Mask
Definition at line 2771 of file core_cm85.h.
| #define MPU_MAIR1_Attr6_Pos 16U |
MPU MAIR1: Attr6 Position
Definition at line 2773 of file core_cm85.h.
| #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) |
MPU MAIR1: Attr6 Mask
Definition at line 2774 of file core_cm85.h.
| #define MPU_MAIR1_Attr5_Pos 8U |
MPU MAIR1: Attr5 Position
Definition at line 2776 of file core_cm85.h.
| #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) |
MPU MAIR1: Attr5 Mask
Definition at line 2777 of file core_cm85.h.
| #define MPU_MAIR1_Attr4_Pos 0U |
MPU MAIR1: Attr4 Position
Definition at line 2779 of file core_cm85.h.
| #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) |
MPU MAIR1: Attr4 Mask
Definition at line 2780 of file core_cm85.h.
| #define FPU_FPCCR_ASPEN_Pos 31U |
FPCCR: ASPEN bit Position
Definition at line 2895 of file core_cm85.h.
| #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) |
FPCCR: ASPEN bit Mask
Definition at line 2896 of file core_cm85.h.
| #define FPU_FPCCR_LSPEN_Pos 30U |
FPCCR: LSPEN Position
Definition at line 2898 of file core_cm85.h.
| #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) |
FPCCR: LSPEN bit Mask
Definition at line 2899 of file core_cm85.h.
| #define FPU_FPCCR_LSPENS_Pos 29U |
FPCCR: LSPENS Position
Definition at line 2901 of file core_cm85.h.
| #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) |
FPCCR: LSPENS bit Mask
Definition at line 2902 of file core_cm85.h.
| #define FPU_FPCCR_CLRONRET_Pos 28U |
FPCCR: CLRONRET Position
Definition at line 2904 of file core_cm85.h.
| #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) |
FPCCR: CLRONRET bit Mask
Definition at line 2905 of file core_cm85.h.
| #define FPU_FPCCR_CLRONRETS_Pos 27U |
FPCCR: CLRONRETS Position
Definition at line 2907 of file core_cm85.h.
| #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) |
FPCCR: CLRONRETS bit Mask
Definition at line 2908 of file core_cm85.h.
| #define FPU_FPCCR_TS_Pos 26U |
FPCCR: TS Position
Definition at line 2910 of file core_cm85.h.
| #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) |
FPCCR: TS bit Mask
Definition at line 2911 of file core_cm85.h.
| #define FPU_FPCCR_UFRDY_Pos 10U |
FPCCR: UFRDY Position
Definition at line 2913 of file core_cm85.h.
| #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) |
FPCCR: UFRDY bit Mask
Definition at line 2914 of file core_cm85.h.
| #define FPU_FPCCR_SPLIMVIOL_Pos 9U |
FPCCR: SPLIMVIOL Position
Definition at line 2916 of file core_cm85.h.
| #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) |
FPCCR: SPLIMVIOL bit Mask
Definition at line 2917 of file core_cm85.h.
| #define FPU_FPCCR_MONRDY_Pos 8U |
FPCCR: MONRDY Position
Definition at line 2919 of file core_cm85.h.
| #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) |
FPCCR: MONRDY bit Mask
Definition at line 2920 of file core_cm85.h.
| #define FPU_FPCCR_SFRDY_Pos 7U |
FPCCR: SFRDY Position
Definition at line 2922 of file core_cm85.h.
| #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) |
FPCCR: SFRDY bit Mask
Definition at line 2923 of file core_cm85.h.
| #define FPU_FPCCR_BFRDY_Pos 6U |
FPCCR: BFRDY Position
Definition at line 2925 of file core_cm85.h.
| #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) |
FPCCR: BFRDY bit Mask
Definition at line 2926 of file core_cm85.h.
| #define FPU_FPCCR_MMRDY_Pos 5U |
FPCCR: MMRDY Position
Definition at line 2928 of file core_cm85.h.
| #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) |
FPCCR: MMRDY bit Mask
Definition at line 2929 of file core_cm85.h.
| #define FPU_FPCCR_HFRDY_Pos 4U |
FPCCR: HFRDY Position
Definition at line 2931 of file core_cm85.h.
| #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) |
FPCCR: HFRDY bit Mask
Definition at line 2932 of file core_cm85.h.
| #define FPU_FPCCR_THREAD_Pos 3U |
FPCCR: processor mode bit Position
Definition at line 2934 of file core_cm85.h.
| #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) |
FPCCR: processor mode active bit Mask
Definition at line 2935 of file core_cm85.h.
| #define FPU_FPCCR_S_Pos 2U |
FPCCR: Security status of the FP context bit Position
Definition at line 2937 of file core_cm85.h.
| #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) |
FPCCR: Security status of the FP context bit Mask
Definition at line 2938 of file core_cm85.h.
| #define FPU_FPCCR_USER_Pos 1U |
FPCCR: privilege level bit Position
Definition at line 2940 of file core_cm85.h.
| #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) |
FPCCR: privilege level bit Mask
Definition at line 2941 of file core_cm85.h.
| #define FPU_FPCCR_LSPACT_Pos 0U |
FPCCR: Lazy state preservation active bit Position
Definition at line 2943 of file core_cm85.h.
| #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) |
FPCCR: Lazy state preservation active bit Mask
Definition at line 2944 of file core_cm85.h.
| #define FPU_FPCAR_ADDRESS_Pos 3U |
FPCAR: ADDRESS bit Position
Definition at line 2947 of file core_cm85.h.
| #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) |
FPCAR: ADDRESS bit Mask
Definition at line 2948 of file core_cm85.h.
| #define FPU_FPDSCR_AHP_Pos 26U |
FPDSCR: AHP bit Position
Definition at line 2951 of file core_cm85.h.
| #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) |
FPDSCR: AHP bit Mask
Definition at line 2952 of file core_cm85.h.
| #define FPU_FPDSCR_DN_Pos 25U |
FPDSCR: DN bit Position
Definition at line 2954 of file core_cm85.h.
| #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) |
FPDSCR: DN bit Mask
Definition at line 2955 of file core_cm85.h.
| #define FPU_FPDSCR_FZ_Pos 24U |
FPDSCR: FZ bit Position
Definition at line 2957 of file core_cm85.h.
| #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) |
FPDSCR: FZ bit Mask
Definition at line 2958 of file core_cm85.h.
| #define FPU_FPDSCR_RMode_Pos 22U |
FPDSCR: RMode bit Position
Definition at line 2960 of file core_cm85.h.
| #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) |
FPDSCR: RMode bit Mask
Definition at line 2961 of file core_cm85.h.
| #define FPU_MVFR2_FPMisc_Pos 4U |
MVFR2: FPMisc bits Position
Definition at line 3008 of file core_cm85.h.
| #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) |
MVFR2: FPMisc bits Mask
Definition at line 3009 of file core_cm85.h.
| #define DCB_DHCSR_DBGKEY_Pos 16U |
DCB DHCSR: Debug key Position
Definition at line 3207 of file core_cm85.h.
| #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) |
DCB DHCSR: Debug key Mask
Definition at line 3208 of file core_cm85.h.
| #define DCB_DHCSR_S_RESTART_ST_Pos 26U |
DCB DHCSR: Restart sticky status Position
Definition at line 3210 of file core_cm85.h.
| #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) |
DCB DHCSR: Restart sticky status Mask
Definition at line 3211 of file core_cm85.h.
| #define DCB_DHCSR_S_RESET_ST_Pos 25U |
DCB DHCSR: Reset sticky status Position
Definition at line 3213 of file core_cm85.h.
| #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) |
DCB DHCSR: Reset sticky status Mask
Definition at line 3214 of file core_cm85.h.
| #define DCB_DHCSR_S_RETIRE_ST_Pos 24U |
DCB DHCSR: Retire sticky status Position
Definition at line 3216 of file core_cm85.h.
| #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) |
DCB DHCSR: Retire sticky status Mask
Definition at line 3217 of file core_cm85.h.
| #define DCB_DHCSR_S_SDE_Pos 20U |
DCB DHCSR: Secure debug enabled Position
Definition at line 3228 of file core_cm85.h.
| #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) |
DCB DHCSR: Secure debug enabled Mask
Definition at line 3229 of file core_cm85.h.
| #define DCB_DHCSR_S_LOCKUP_Pos 19U |
DCB DHCSR: Lockup status Position
Definition at line 3231 of file core_cm85.h.
| #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) |
DCB DHCSR: Lockup status Mask
Definition at line 3232 of file core_cm85.h.
| #define DCB_DHCSR_S_SLEEP_Pos 18U |
DCB DHCSR: Sleeping status Position
Definition at line 3234 of file core_cm85.h.
| #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) |
DCB DHCSR: Sleeping status Mask
Definition at line 3235 of file core_cm85.h.
| #define DCB_DHCSR_S_HALT_Pos 17U |
DCB DHCSR: Halted status Position
Definition at line 3237 of file core_cm85.h.
| #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) |
DCB DHCSR: Halted status Mask
Definition at line 3238 of file core_cm85.h.
| #define DCB_DHCSR_S_REGRDY_Pos 16U |
DCB DHCSR: Register ready status Position
Definition at line 3240 of file core_cm85.h.
| #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) |
DCB DHCSR: Register ready status Mask
Definition at line 3241 of file core_cm85.h.
| #define DCB_DHCSR_C_SNAPSTALL_Pos 5U |
DCB DHCSR: Snap stall control Position
Definition at line 3246 of file core_cm85.h.
| #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) |
DCB DHCSR: Snap stall control Mask
Definition at line 3247 of file core_cm85.h.
| #define DCB_DHCSR_C_MASKINTS_Pos 3U |
DCB DHCSR: Mask interrupts control Position
Definition at line 3249 of file core_cm85.h.
| #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) |
DCB DHCSR: Mask interrupts control Mask
Definition at line 3250 of file core_cm85.h.
| #define DCB_DHCSR_C_STEP_Pos 2U |
DCB DHCSR: Step control Position
Definition at line 3252 of file core_cm85.h.
| #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) |
DCB DHCSR: Step control Mask
Definition at line 3253 of file core_cm85.h.
| #define DCB_DHCSR_C_HALT_Pos 1U |
DCB DHCSR: Halt control Position
Definition at line 3255 of file core_cm85.h.
| #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) |
DCB DHCSR: Halt control Mask
Definition at line 3256 of file core_cm85.h.
| #define DCB_DHCSR_C_DEBUGEN_Pos 0U |
DCB DHCSR: Debug enable control Position
Definition at line 3258 of file core_cm85.h.
| #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) |
DCB DHCSR: Debug enable control Mask
Definition at line 3259 of file core_cm85.h.
| #define DCB_DCRSR_REGWnR_Pos 16U |
DCB DCRSR: Register write/not-read Position
Definition at line 3262 of file core_cm85.h.
| #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) |
DCB DCRSR: Register write/not-read Mask
Definition at line 3263 of file core_cm85.h.
| #define DCB_DCRSR_REGSEL_Pos 0U |
DCB DCRSR: Register selector Position
Definition at line 3265 of file core_cm85.h.
| #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) |
DCB DCRSR: Register selector Mask
Definition at line 3266 of file core_cm85.h.
| #define DCB_DCRDR_DBGTMP_Pos 0U |
DCB DCRDR: Data temporary buffer Position
Definition at line 3269 of file core_cm85.h.
| #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) |
DCB DCRDR: Data temporary buffer Mask
Definition at line 3270 of file core_cm85.h.
| #define DCB_DEMCR_TRCENA_Pos 24U |
DCB DEMCR: Trace enable Position
Definition at line 3273 of file core_cm85.h.
| #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) |
DCB DEMCR: Trace enable Mask
Definition at line 3274 of file core_cm85.h.
| #define DCB_DEMCR_MONPRKEY_Pos 23U |
DCB DEMCR: Monitor pend req key Position
Definition at line 3276 of file core_cm85.h.
| #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) |
DCB DEMCR: Monitor pend req key Mask
Definition at line 3277 of file core_cm85.h.
| #define DCB_DEMCR_UMON_EN_Pos 21U |
DCB DEMCR: Unprivileged monitor enable Position
Definition at line 3279 of file core_cm85.h.
| #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) |
DCB DEMCR: Unprivileged monitor enable Mask
Definition at line 3280 of file core_cm85.h.
| #define DCB_DEMCR_SDME_Pos 20U |
DCB DEMCR: Secure DebugMonitor enable Position
Definition at line 3282 of file core_cm85.h.
| #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) |
DCB DEMCR: Secure DebugMonitor enable Mask
Definition at line 3283 of file core_cm85.h.
| #define DCB_DEMCR_MON_REQ_Pos 19U |
DCB DEMCR: Monitor request Position
Definition at line 3285 of file core_cm85.h.
| #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) |
DCB DEMCR: Monitor request Mask
Definition at line 3286 of file core_cm85.h.
| #define DCB_DEMCR_MON_STEP_Pos 18U |
DCB DEMCR: Monitor step Position
Definition at line 3288 of file core_cm85.h.
| #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) |
DCB DEMCR: Monitor step Mask
Definition at line 3289 of file core_cm85.h.
| #define DCB_DEMCR_MON_PEND_Pos 17U |
DCB DEMCR: Monitor pend Position
Definition at line 3291 of file core_cm85.h.
| #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) |
DCB DEMCR: Monitor pend Mask
Definition at line 3292 of file core_cm85.h.
| #define DCB_DEMCR_MON_EN_Pos 16U |
DCB DEMCR: Monitor enable Position
Definition at line 3294 of file core_cm85.h.
| #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) |
DCB DEMCR: Monitor enable Mask
Definition at line 3295 of file core_cm85.h.
| #define DCB_DEMCR_VC_SFERR_Pos 11U |
DCB DEMCR: Vector Catch SecureFault Position
Definition at line 3297 of file core_cm85.h.
| #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) |
DCB DEMCR: Vector Catch SecureFault Mask
Definition at line 3298 of file core_cm85.h.
| #define DCB_DEMCR_VC_HARDERR_Pos 10U |
DCB DEMCR: Vector Catch HardFault errors Position
Definition at line 3300 of file core_cm85.h.
| #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) |
DCB DEMCR: Vector Catch HardFault errors Mask
Definition at line 3301 of file core_cm85.h.
| #define DCB_DEMCR_VC_INTERR_Pos 9U |
DCB DEMCR: Vector Catch interrupt errors Position
Definition at line 3303 of file core_cm85.h.
| #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) |
DCB DEMCR: Vector Catch interrupt errors Mask
Definition at line 3304 of file core_cm85.h.
| #define DCB_DEMCR_VC_BUSERR_Pos 8U |
DCB DEMCR: Vector Catch BusFault errors Position
Definition at line 3306 of file core_cm85.h.
| #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) |
DCB DEMCR: Vector Catch BusFault errors Mask
Definition at line 3307 of file core_cm85.h.
| #define DCB_DEMCR_VC_STATERR_Pos 7U |
DCB DEMCR: Vector Catch state errors Position
Definition at line 3309 of file core_cm85.h.
| #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) |
DCB DEMCR: Vector Catch state errors Mask
Definition at line 3310 of file core_cm85.h.
| #define DCB_DEMCR_VC_CHKERR_Pos 6U |
DCB DEMCR: Vector Catch check errors Position
Definition at line 3312 of file core_cm85.h.
| #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) |
DCB DEMCR: Vector Catch check errors Mask
Definition at line 3313 of file core_cm85.h.
| #define DCB_DEMCR_VC_NOCPERR_Pos 5U |
DCB DEMCR: Vector Catch NOCP errors Position
Definition at line 3315 of file core_cm85.h.
| #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) |
DCB DEMCR: Vector Catch NOCP errors Mask
Definition at line 3316 of file core_cm85.h.
| #define DCB_DEMCR_VC_MMERR_Pos 4U |
DCB DEMCR: Vector Catch MemManage errors Position
Definition at line 3318 of file core_cm85.h.
| #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) |
DCB DEMCR: Vector Catch MemManage errors Mask
Definition at line 3319 of file core_cm85.h.
| #define DCB_DEMCR_VC_CORERESET_Pos 0U |
DCB DEMCR: Vector Catch Core reset Position
Definition at line 3321 of file core_cm85.h.
| #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) |
DCB DEMCR: Vector Catch Core reset Mask
Definition at line 3322 of file core_cm85.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position
Definition at line 3347 of file core_cm85.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask
Definition at line 3348 of file core_cm85.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U |
DCB DAUTHCTRL: Secure non-invasive debug enable select Position
Definition at line 3350 of file core_cm85.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) |
DCB DAUTHCTRL: Secure non-invasive debug enable select Mask
Definition at line 3351 of file core_cm85.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U |
DCB DAUTHCTRL: Internal Secure invasive debug enable Position
Definition at line 3353 of file core_cm85.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure invasive debug enable Mask
Definition at line 3354 of file core_cm85.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U |
DCB DAUTHCTRL: Secure invasive debug enable select Position
Definition at line 3356 of file core_cm85.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) |
DCB DAUTHCTRL: Secure invasive debug enable select Mask
Definition at line 3357 of file core_cm85.h.
| #define DCB_DSCSR_CDSKEY_Pos 17U |
DCB DSCSR: CDS write-enable key Position
Definition at line 3360 of file core_cm85.h.
| #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) |
DCB DSCSR: CDS write-enable key Mask
Definition at line 3361 of file core_cm85.h.
| #define DCB_DSCSR_CDS_Pos 16U |
DCB DSCSR: Current domain Secure Position
Definition at line 3363 of file core_cm85.h.
| #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) |
DCB DSCSR: Current domain Secure Mask
Definition at line 3364 of file core_cm85.h.
| #define DCB_DSCSR_SBRSEL_Pos 1U |
DCB DSCSR: Secure banked register select Position
Definition at line 3366 of file core_cm85.h.
| #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) |
DCB DSCSR: Secure banked register select Mask
Definition at line 3367 of file core_cm85.h.
| #define DCB_DSCSR_SBRSELEN_Pos 0U |
DCB DSCSR: Secure banked register select enable Position
Definition at line 3369 of file core_cm85.h.
| #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) |
DCB DSCSR: Secure banked register select enable Mask
Definition at line 3370 of file core_cm85.h.
| #define DIB_DLAR_KEY_Pos 0U |
DIB DLAR: KEY Position
Definition at line 3396 of file core_cm85.h.
| #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) |
DIB DLAR: KEY Mask
Definition at line 3397 of file core_cm85.h.
| #define DIB_DLSR_nTT_Pos 2U |
DIB DLSR: Not thirty-two bit Position
Definition at line 3400 of file core_cm85.h.
| #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) |
DIB DLSR: Not thirty-two bit Mask
Definition at line 3401 of file core_cm85.h.
| #define DIB_DLSR_SLK_Pos 1U |
DIB DLSR: Software Lock status Position
Definition at line 3403 of file core_cm85.h.
| #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) |
DIB DLSR: Software Lock status Mask
Definition at line 3404 of file core_cm85.h.
| #define DIB_DLSR_SLI_Pos 0U |
DIB DLSR: Software Lock implemented Position
Definition at line 3406 of file core_cm85.h.
| #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) |
DIB DLSR: Software Lock implemented Mask
Definition at line 3407 of file core_cm85.h.
| #define DIB_DAUTHSTATUS_SNID_Pos 6U |
DIB DAUTHSTATUS: Secure Non-invasive Debug Position
Definition at line 3422 of file core_cm85.h.
| #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) |
DIB DAUTHSTATUS: Secure Non-invasive Debug Mask
Definition at line 3423 of file core_cm85.h.
| #define DIB_DAUTHSTATUS_SID_Pos 4U |
DIB DAUTHSTATUS: Secure Invasive Debug Position
Definition at line 3425 of file core_cm85.h.
| #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) |
DIB DAUTHSTATUS: Secure Invasive Debug Mask
Definition at line 3426 of file core_cm85.h.
| #define DIB_DAUTHSTATUS_NSNID_Pos 2U |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position
Definition at line 3428 of file core_cm85.h.
| #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask
Definition at line 3429 of file core_cm85.h.
| #define DIB_DAUTHSTATUS_NSID_Pos 0U |
DIB DAUTHSTATUS: Non-secure Invasive Debug Position
Definition at line 3431 of file core_cm85.h.
| #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) |
DIB DAUTHSTATUS: Non-secure Invasive Debug Mask
Definition at line 3432 of file core_cm85.h.
| #define DIB_DDEVARCH_ARCHITECT_Pos 21U |
DIB DDEVARCH: Architect Position
Definition at line 3435 of file core_cm85.h.
| #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) |
DIB DDEVARCH: Architect Mask
Definition at line 3436 of file core_cm85.h.
| #define DIB_DDEVARCH_PRESENT_Pos 20U |
DIB DDEVARCH: DEVARCH Present Position
Definition at line 3438 of file core_cm85.h.
| #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) |
DIB DDEVARCH: DEVARCH Present Mask
Definition at line 3439 of file core_cm85.h.
| #define DIB_DDEVARCH_REVISION_Pos 16U |
DIB DDEVARCH: Revision Position
Definition at line 3441 of file core_cm85.h.
| #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) |
DIB DDEVARCH: Revision Mask
Definition at line 3442 of file core_cm85.h.
| #define DIB_DDEVARCH_ARCHVER_Pos 12U |
DIB DDEVARCH: Architecture Version Position
Definition at line 3444 of file core_cm85.h.
| #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) |
DIB DDEVARCH: Architecture Version Mask
Definition at line 3445 of file core_cm85.h.
| #define DIB_DDEVARCH_ARCHPART_Pos 0U |
DIB DDEVARCH: Architecture Part Position
Definition at line 3447 of file core_cm85.h.
| #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) |
DIB DDEVARCH: Architecture Part Mask
Definition at line 3448 of file core_cm85.h.
| #define DIB_DDEVTYPE_SUB_Pos 4U |
DIB DDEVTYPE: Sub-type Position
Definition at line 3451 of file core_cm85.h.
| #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) |
DIB DDEVTYPE: Sub-type Mask
Definition at line 3452 of file core_cm85.h.
| #define DIB_DDEVTYPE_MAJOR_Pos 0U |
DIB DDEVTYPE: Major type Position
Definition at line 3454 of file core_cm85.h.
| #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) |
DIB DDEVTYPE: Major type Mask
Definition at line 3455 of file core_cm85.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 3474 of file core_cm85.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 3482 of file core_cm85.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 3495 of file core_cm85.h.
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
Definition at line 3496 of file core_cm85.h.
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
Definition at line 3497 of file core_cm85.h.
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
Definition at line 3503 of file core_cm85.h.
| #define DCB_BASE (0xE000EDF0UL) |
DCB Base Address
Definition at line 3505 of file core_cm85.h.
| #define DIB_BASE (0xE000EFB0UL) |
DIB Base Address
Definition at line 3506 of file core_cm85.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 3507 of file core_cm85.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 3508 of file core_cm85.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 3509 of file core_cm85.h.
SCB configuration struct
Definition at line 3512 of file core_cm85.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 3513 of file core_cm85.h.
NVIC configuration struct
Definition at line 3514 of file core_cm85.h.
ITM configuration struct
Definition at line 3515 of file core_cm85.h.
DWT configuration struct
Definition at line 3516 of file core_cm85.h.
TPI configuration struct
Definition at line 3517 of file core_cm85.h.
DCB configuration struct
Definition at line 3524 of file core_cm85.h.
DIB configuration struct
Definition at line 3525 of file core_cm85.h.
| #define MPU_BASE (SCS_BASE + 0x0D90UL) |
Memory Protection Unit
Definition at line 3528 of file core_cm85.h.
Memory Protection Unit
Definition at line 3529 of file core_cm85.h.
| #define FPU_BASE (SCS_BASE + 0x0F30UL) |
Floating Point Unit
Definition at line 3542 of file core_cm85.h.
Floating Point Unit
Definition at line 3543 of file core_cm85.h.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 4596 of file core_cm85.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 368 of file core_sc000.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 369 of file core_sc000.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 371 of file core_sc000.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 372 of file core_sc000.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 374 of file core_sc000.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 375 of file core_sc000.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 377 of file core_sc000.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 378 of file core_sc000.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 380 of file core_sc000.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 381 of file core_sc000.h.
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
Definition at line 384 of file core_sc000.h.
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
Definition at line 385 of file core_sc000.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 387 of file core_sc000.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 388 of file core_sc000.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 390 of file core_sc000.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 391 of file core_sc000.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 393 of file core_sc000.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 394 of file core_sc000.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 396 of file core_sc000.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 397 of file core_sc000.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 399 of file core_sc000.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 400 of file core_sc000.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 402 of file core_sc000.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 403 of file core_sc000.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 405 of file core_sc000.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 406 of file core_sc000.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 408 of file core_sc000.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 409 of file core_sc000.h.
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
Definition at line 412 of file core_sc000.h.
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
Definition at line 413 of file core_sc000.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 416 of file core_sc000.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 417 of file core_sc000.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 419 of file core_sc000.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 420 of file core_sc000.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 422 of file core_sc000.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 423 of file core_sc000.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 425 of file core_sc000.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 426 of file core_sc000.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 428 of file core_sc000.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 429 of file core_sc000.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 432 of file core_sc000.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 433 of file core_sc000.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 435 of file core_sc000.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 436 of file core_sc000.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 438 of file core_sc000.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 439 of file core_sc000.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 445 of file core_sc000.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 446 of file core_sc000.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 449 of file core_sc000.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 450 of file core_sc000.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 497 of file core_sc000.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 498 of file core_sc000.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 500 of file core_sc000.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 501 of file core_sc000.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 503 of file core_sc000.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 504 of file core_sc000.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 506 of file core_sc000.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 507 of file core_sc000.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 510 of file core_sc000.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 511 of file core_sc000.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 514 of file core_sc000.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 515 of file core_sc000.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 518 of file core_sc000.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 519 of file core_sc000.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 521 of file core_sc000.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 522 of file core_sc000.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 524 of file core_sc000.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 525 of file core_sc000.h.
| #define MPU_TYPE_IREGION_Pos 16U |
MPU TYPE: IREGION Position
Definition at line 550 of file core_sc000.h.
| #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) |
MPU TYPE: IREGION Mask
Definition at line 551 of file core_sc000.h.
| #define MPU_TYPE_DREGION_Pos 8U |
MPU TYPE: DREGION Position
Definition at line 553 of file core_sc000.h.
| #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) |
MPU TYPE: DREGION Mask
Definition at line 554 of file core_sc000.h.
| #define MPU_TYPE_SEPARATE_Pos 0U |
MPU TYPE: SEPARATE Position
Definition at line 556 of file core_sc000.h.
| #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) |
MPU TYPE: SEPARATE Mask
Definition at line 557 of file core_sc000.h.
| #define MPU_CTRL_PRIVDEFENA_Pos 2U |
MPU CTRL: PRIVDEFENA Position
Definition at line 560 of file core_sc000.h.
| #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) |
MPU CTRL: PRIVDEFENA Mask
Definition at line 561 of file core_sc000.h.
| #define MPU_CTRL_HFNMIENA_Pos 1U |
MPU CTRL: HFNMIENA Position
Definition at line 563 of file core_sc000.h.
| #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) |
MPU CTRL: HFNMIENA Mask
Definition at line 564 of file core_sc000.h.
| #define MPU_CTRL_ENABLE_Pos 0U |
MPU CTRL: ENABLE Position
Definition at line 566 of file core_sc000.h.
| #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) |
MPU CTRL: ENABLE Mask
Definition at line 567 of file core_sc000.h.
| #define MPU_RNR_REGION_Pos 0U |
MPU RNR: REGION Position
Definition at line 570 of file core_sc000.h.
| #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) |
MPU RNR: REGION Mask
Definition at line 571 of file core_sc000.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 641 of file core_sc000.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 649 of file core_sc000.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 662 of file core_sc000.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 663 of file core_sc000.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 664 of file core_sc000.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 665 of file core_sc000.h.
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
Definition at line 667 of file core_sc000.h.
SCB configuration struct
Definition at line 668 of file core_sc000.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 669 of file core_sc000.h.
NVIC configuration struct
Definition at line 670 of file core_sc000.h.
| #define MPU_BASE (SCS_BASE + 0x0D90UL) |
Memory Protection Unit
Definition at line 673 of file core_sc000.h.
Memory Protection Unit
Definition at line 674 of file core_sc000.h.
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
Definition at line 363 of file core_sc300.h.
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
Definition at line 364 of file core_sc300.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 407 of file core_sc300.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 408 of file core_sc300.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 410 of file core_sc300.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 411 of file core_sc300.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 413 of file core_sc300.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 414 of file core_sc300.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 416 of file core_sc300.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 417 of file core_sc300.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 419 of file core_sc300.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 420 of file core_sc300.h.
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
Definition at line 423 of file core_sc300.h.
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
Definition at line 424 of file core_sc300.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 426 of file core_sc300.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 427 of file core_sc300.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 429 of file core_sc300.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 430 of file core_sc300.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 432 of file core_sc300.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 433 of file core_sc300.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 435 of file core_sc300.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 436 of file core_sc300.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 438 of file core_sc300.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 439 of file core_sc300.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 441 of file core_sc300.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 442 of file core_sc300.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 444 of file core_sc300.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 445 of file core_sc300.h.
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
Definition at line 447 of file core_sc300.h.
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
Definition at line 448 of file core_sc300.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 450 of file core_sc300.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 451 of file core_sc300.h.
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
Definition at line 457 of file core_sc300.h.
| #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
Definition at line 458 of file core_sc300.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 461 of file core_sc300.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 462 of file core_sc300.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 464 of file core_sc300.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 465 of file core_sc300.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 467 of file core_sc300.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 468 of file core_sc300.h.
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
Definition at line 470 of file core_sc300.h.
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
Definition at line 471 of file core_sc300.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 473 of file core_sc300.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 474 of file core_sc300.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 476 of file core_sc300.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 477 of file core_sc300.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 483 of file core_sc300.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 484 of file core_sc300.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 486 of file core_sc300.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 487 of file core_sc300.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 489 of file core_sc300.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 490 of file core_sc300.h.
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
Definition at line 496 of file core_sc300.h.
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
Definition at line 497 of file core_sc300.h.
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
Definition at line 499 of file core_sc300.h.
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
Definition at line 500 of file core_sc300.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 502 of file core_sc300.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 503 of file core_sc300.h.
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
Definition at line 505 of file core_sc300.h.
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
Definition at line 506 of file core_sc300.h.
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
Definition at line 512 of file core_sc300.h.
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
Definition at line 513 of file core_sc300.h.
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
Definition at line 515 of file core_sc300.h.
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
Definition at line 516 of file core_sc300.h.
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
Definition at line 518 of file core_sc300.h.
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
Definition at line 519 of file core_sc300.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 521 of file core_sc300.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 522 of file core_sc300.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
Definition at line 524 of file core_sc300.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
Definition at line 525 of file core_sc300.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
Definition at line 527 of file core_sc300.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
Definition at line 528 of file core_sc300.h.
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
Definition at line 530 of file core_sc300.h.
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
Definition at line 531 of file core_sc300.h.
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
Definition at line 533 of file core_sc300.h.
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
Definition at line 534 of file core_sc300.h.
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
Definition at line 536 of file core_sc300.h.
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
Definition at line 537 of file core_sc300.h.
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
Definition at line 539 of file core_sc300.h.
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
Definition at line 540 of file core_sc300.h.
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
Definition at line 542 of file core_sc300.h.
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
Definition at line 543 of file core_sc300.h.
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
Definition at line 545 of file core_sc300.h.
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
Definition at line 546 of file core_sc300.h.
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
Definition at line 548 of file core_sc300.h.
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
Definition at line 549 of file core_sc300.h.
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
Definition at line 551 of file core_sc300.h.
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
Definition at line 552 of file core_sc300.h.
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
Definition at line 555 of file core_sc300.h.
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
Definition at line 556 of file core_sc300.h.
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
Definition at line 558 of file core_sc300.h.
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
Definition at line 559 of file core_sc300.h.
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
Definition at line 561 of file core_sc300.h.
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
Definition at line 562 of file core_sc300.h.
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
Definition at line 565 of file core_sc300.h.
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
Definition at line 566 of file core_sc300.h.
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
Definition at line 568 of file core_sc300.h.
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
Definition at line 569 of file core_sc300.h.
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
Definition at line 571 of file core_sc300.h.
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
Definition at line 572 of file core_sc300.h.
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
Definition at line 574 of file core_sc300.h.
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
Definition at line 575 of file core_sc300.h.
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
Definition at line 577 of file core_sc300.h.
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
Definition at line 578 of file core_sc300.h.
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
Definition at line 581 of file core_sc300.h.
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
Definition at line 582 of file core_sc300.h.
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
Definition at line 584 of file core_sc300.h.
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
Definition at line 585 of file core_sc300.h.
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
Definition at line 587 of file core_sc300.h.
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
Definition at line 588 of file core_sc300.h.
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
Definition at line 590 of file core_sc300.h.
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
Definition at line 591 of file core_sc300.h.
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
Definition at line 593 of file core_sc300.h.
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
Definition at line 594 of file core_sc300.h.
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
Definition at line 596 of file core_sc300.h.
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
Definition at line 597 of file core_sc300.h.
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
Definition at line 600 of file core_sc300.h.
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
Definition at line 601 of file core_sc300.h.
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
Definition at line 603 of file core_sc300.h.
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
Definition at line 604 of file core_sc300.h.
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
Definition at line 606 of file core_sc300.h.
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
Definition at line 607 of file core_sc300.h.
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
Definition at line 609 of file core_sc300.h.
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
Definition at line 610 of file core_sc300.h.
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
Definition at line 612 of file core_sc300.h.
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
Definition at line 613 of file core_sc300.h.
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
Definition at line 615 of file core_sc300.h.
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
Definition at line 616 of file core_sc300.h.
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
Definition at line 619 of file core_sc300.h.
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
Definition at line 620 of file core_sc300.h.
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
Definition at line 622 of file core_sc300.h.
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
Definition at line 623 of file core_sc300.h.
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
Definition at line 625 of file core_sc300.h.
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
Definition at line 626 of file core_sc300.h.
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
Definition at line 629 of file core_sc300.h.
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
Definition at line 630 of file core_sc300.h.
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
Definition at line 632 of file core_sc300.h.
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
Definition at line 633 of file core_sc300.h.
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
Definition at line 635 of file core_sc300.h.
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
Definition at line 636 of file core_sc300.h.
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
Definition at line 638 of file core_sc300.h.
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
Definition at line 639 of file core_sc300.h.
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
Definition at line 641 of file core_sc300.h.
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
Definition at line 642 of file core_sc300.h.
| #define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
Definition at line 665 of file core_sc300.h.
| #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
Definition at line 666 of file core_sc300.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 700 of file core_sc300.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 701 of file core_sc300.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 703 of file core_sc300.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 704 of file core_sc300.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 706 of file core_sc300.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 707 of file core_sc300.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 709 of file core_sc300.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 710 of file core_sc300.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 713 of file core_sc300.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 714 of file core_sc300.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 717 of file core_sc300.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 718 of file core_sc300.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 721 of file core_sc300.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 722 of file core_sc300.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 724 of file core_sc300.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 725 of file core_sc300.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 727 of file core_sc300.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 728 of file core_sc300.h.
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
Definition at line 777 of file core_sc300.h.
| #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
Definition at line 778 of file core_sc300.h.
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
Definition at line 781 of file core_sc300.h.
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
Definition at line 782 of file core_sc300.h.
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
Definition at line 787 of file core_sc300.h.
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
Definition at line 788 of file core_sc300.h.
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
Definition at line 793 of file core_sc300.h.
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
Definition at line 794 of file core_sc300.h.
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
Definition at line 796 of file core_sc300.h.
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
Definition at line 797 of file core_sc300.h.
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
Definition at line 799 of file core_sc300.h.
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
Definition at line 800 of file core_sc300.h.
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
Definition at line 802 of file core_sc300.h.
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
Definition at line 803 of file core_sc300.h.
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
Definition at line 805 of file core_sc300.h.
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
Definition at line 806 of file core_sc300.h.
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
Definition at line 809 of file core_sc300.h.
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
Definition at line 810 of file core_sc300.h.
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
Definition at line 812 of file core_sc300.h.
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
Definition at line 813 of file core_sc300.h.
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
Definition at line 815 of file core_sc300.h.
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
Definition at line 816 of file core_sc300.h.
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
Definition at line 859 of file core_sc300.h.
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
Definition at line 860 of file core_sc300.h.
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
Definition at line 862 of file core_sc300.h.
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
Definition at line 863 of file core_sc300.h.
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
Definition at line 865 of file core_sc300.h.
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
Definition at line 866 of file core_sc300.h.
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
Definition at line 868 of file core_sc300.h.
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
Definition at line 869 of file core_sc300.h.
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
Definition at line 871 of file core_sc300.h.
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
Definition at line 872 of file core_sc300.h.
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
Definition at line 874 of file core_sc300.h.
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
Definition at line 875 of file core_sc300.h.
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
Definition at line 877 of file core_sc300.h.
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
Definition at line 878 of file core_sc300.h.
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
Definition at line 880 of file core_sc300.h.
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
Definition at line 881 of file core_sc300.h.
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
Definition at line 883 of file core_sc300.h.
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
Definition at line 884 of file core_sc300.h.
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
Definition at line 886 of file core_sc300.h.
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
Definition at line 887 of file core_sc300.h.
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
Definition at line 889 of file core_sc300.h.
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
Definition at line 890 of file core_sc300.h.
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
Definition at line 892 of file core_sc300.h.
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
Definition at line 893 of file core_sc300.h.
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
Definition at line 895 of file core_sc300.h.
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
Definition at line 896 of file core_sc300.h.
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
Definition at line 898 of file core_sc300.h.
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
Definition at line 899 of file core_sc300.h.
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
Definition at line 901 of file core_sc300.h.
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
Definition at line 902 of file core_sc300.h.
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
Definition at line 904 of file core_sc300.h.
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
Definition at line 905 of file core_sc300.h.
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
Definition at line 907 of file core_sc300.h.
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
Definition at line 908 of file core_sc300.h.
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
Definition at line 910 of file core_sc300.h.
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
Definition at line 911 of file core_sc300.h.
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
Definition at line 914 of file core_sc300.h.
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
Definition at line 915 of file core_sc300.h.
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
Definition at line 918 of file core_sc300.h.
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
Definition at line 919 of file core_sc300.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
Definition at line 922 of file core_sc300.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
Definition at line 923 of file core_sc300.h.
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
Definition at line 926 of file core_sc300.h.
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
Definition at line 927 of file core_sc300.h.
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
Definition at line 930 of file core_sc300.h.
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
Definition at line 931 of file core_sc300.h.
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
Definition at line 938 of file core_sc300.h.
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
Definition at line 939 of file core_sc300.h.
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
Definition at line 947 of file core_sc300.h.
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
Definition at line 948 of file core_sc300.h.
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
Definition at line 1007 of file core_sc300.h.
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
Definition at line 1008 of file core_sc300.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 1011 of file core_sc300.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 1012 of file core_sc300.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 1015 of file core_sc300.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 1016 of file core_sc300.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 1018 of file core_sc300.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 1019 of file core_sc300.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 1021 of file core_sc300.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 1022 of file core_sc300.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 1024 of file core_sc300.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 1025 of file core_sc300.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 1028 of file core_sc300.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 1029 of file core_sc300.h.
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
Definition at line 1031 of file core_sc300.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 1032 of file core_sc300.h.
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
Definition at line 1035 of file core_sc300.h.
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
Definition at line 1036 of file core_sc300.h.
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
Definition at line 1097 of file core_sc300.h.
| #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
Definition at line 1098 of file core_sc300.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 1101 of file core_sc300.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1102 of file core_sc300.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 1104 of file core_sc300.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1105 of file core_sc300.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 1107 of file core_sc300.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1108 of file core_sc300.h.
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
Definition at line 1116 of file core_sc300.h.
| #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
Definition at line 1117 of file core_sc300.h.
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
Definition at line 1120 of file core_sc300.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 1121 of file core_sc300.h.
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
Definition at line 1123 of file core_sc300.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1124 of file core_sc300.h.
| #define MPU_TYPE_IREGION_Pos 16U |
MPU TYPE: IREGION Position
Definition at line 1156 of file core_sc300.h.
| #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) |
MPU TYPE: IREGION Mask
Definition at line 1157 of file core_sc300.h.
| #define MPU_TYPE_DREGION_Pos 8U |
MPU TYPE: DREGION Position
Definition at line 1159 of file core_sc300.h.
| #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) |
MPU TYPE: DREGION Mask
Definition at line 1160 of file core_sc300.h.
| #define MPU_TYPE_SEPARATE_Pos 0U |
MPU TYPE: SEPARATE Position
Definition at line 1162 of file core_sc300.h.
| #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) |
MPU TYPE: SEPARATE Mask
Definition at line 1163 of file core_sc300.h.
| #define MPU_CTRL_PRIVDEFENA_Pos 2U |
MPU CTRL: PRIVDEFENA Position
Definition at line 1166 of file core_sc300.h.
| #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) |
MPU CTRL: PRIVDEFENA Mask
Definition at line 1167 of file core_sc300.h.
| #define MPU_CTRL_HFNMIENA_Pos 1U |
MPU CTRL: HFNMIENA Position
Definition at line 1169 of file core_sc300.h.
| #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) |
MPU CTRL: HFNMIENA Mask
Definition at line 1170 of file core_sc300.h.
| #define MPU_CTRL_ENABLE_Pos 0U |
MPU CTRL: ENABLE Position
Definition at line 1172 of file core_sc300.h.
| #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) |
MPU CTRL: ENABLE Mask
Definition at line 1173 of file core_sc300.h.
| #define MPU_RNR_REGION_Pos 0U |
MPU RNR: REGION Position
Definition at line 1176 of file core_sc300.h.
| #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) |
MPU RNR: REGION Mask
Definition at line 1177 of file core_sc300.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 1342 of file core_sc300.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 1350 of file core_sc300.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 1363 of file core_sc300.h.
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
Definition at line 1364 of file core_sc300.h.
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
Definition at line 1365 of file core_sc300.h.
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
Definition at line 1366 of file core_sc300.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 1368 of file core_sc300.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 1369 of file core_sc300.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 1370 of file core_sc300.h.
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
Definition at line 1372 of file core_sc300.h.
SCB configuration struct
Definition at line 1373 of file core_sc300.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 1374 of file core_sc300.h.
NVIC configuration struct
Definition at line 1375 of file core_sc300.h.
ITM configuration struct
Definition at line 1376 of file core_sc300.h.
DWT configuration struct
Definition at line 1377 of file core_sc300.h.
TPI configuration struct
Definition at line 1378 of file core_sc300.h.
| #define MPU_BASE (SCS_BASE + 0x0D90UL) |
Memory Protection Unit
Definition at line 1382 of file core_sc300.h.
Memory Protection Unit
Definition at line 1383 of file core_sc300.h.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 1841 of file core_sc300.h.
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
Definition at line 494 of file core_starmc1.h.
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
Definition at line 495 of file core_starmc1.h.
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
Definition at line 568 of file core_starmc1.h.
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
Definition at line 569 of file core_starmc1.h.
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
Definition at line 571 of file core_starmc1.h.
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
Definition at line 572 of file core_starmc1.h.
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
Definition at line 574 of file core_starmc1.h.
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
Definition at line 575 of file core_starmc1.h.
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
Definition at line 577 of file core_starmc1.h.
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
Definition at line 578 of file core_starmc1.h.
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
Definition at line 580 of file core_starmc1.h.
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
Definition at line 581 of file core_starmc1.h.
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
Definition at line 584 of file core_starmc1.h.
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
Definition at line 585 of file core_starmc1.h.
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
Definition at line 587 of file core_starmc1.h.
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
Definition at line 588 of file core_starmc1.h.
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
Definition at line 590 of file core_starmc1.h.
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
Definition at line 591 of file core_starmc1.h.
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
Definition at line 593 of file core_starmc1.h.
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
Definition at line 594 of file core_starmc1.h.
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
Definition at line 596 of file core_starmc1.h.
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Definition at line 597 of file core_starmc1.h.
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
Definition at line 599 of file core_starmc1.h.
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
Definition at line 600 of file core_starmc1.h.
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
Definition at line 602 of file core_starmc1.h.
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Definition at line 603 of file core_starmc1.h.
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
Definition at line 605 of file core_starmc1.h.
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
Definition at line 606 of file core_starmc1.h.
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
Definition at line 608 of file core_starmc1.h.
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
Definition at line 609 of file core_starmc1.h.
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
Definition at line 611 of file core_starmc1.h.
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Definition at line 612 of file core_starmc1.h.
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
Definition at line 614 of file core_starmc1.h.
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
Definition at line 615 of file core_starmc1.h.
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
Definition at line 617 of file core_starmc1.h.
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
Definition at line 618 of file core_starmc1.h.
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
Definition at line 620 of file core_starmc1.h.
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
Definition at line 621 of file core_starmc1.h.
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
Definition at line 624 of file core_starmc1.h.
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
Definition at line 625 of file core_starmc1.h.
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
Definition at line 628 of file core_starmc1.h.
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Definition at line 629 of file core_starmc1.h.
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
Definition at line 631 of file core_starmc1.h.
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
Definition at line 632 of file core_starmc1.h.
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
Definition at line 634 of file core_starmc1.h.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
Definition at line 635 of file core_starmc1.h.
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
Definition at line 637 of file core_starmc1.h.
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
Definition at line 638 of file core_starmc1.h.
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
Definition at line 640 of file core_starmc1.h.
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
Definition at line 641 of file core_starmc1.h.
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
Definition at line 643 of file core_starmc1.h.
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
Definition at line 644 of file core_starmc1.h.
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
Definition at line 646 of file core_starmc1.h.
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
Definition at line 647 of file core_starmc1.h.
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
Definition at line 649 of file core_starmc1.h.
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Definition at line 650 of file core_starmc1.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
Definition at line 652 of file core_starmc1.h.
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
Definition at line 653 of file core_starmc1.h.
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
Definition at line 656 of file core_starmc1.h.
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
Definition at line 657 of file core_starmc1.h.
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
Definition at line 659 of file core_starmc1.h.
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
Definition at line 660 of file core_starmc1.h.
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
Definition at line 662 of file core_starmc1.h.
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
Definition at line 663 of file core_starmc1.h.
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
Definition at line 665 of file core_starmc1.h.
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
Definition at line 666 of file core_starmc1.h.
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
Definition at line 669 of file core_starmc1.h.
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
Definition at line 670 of file core_starmc1.h.
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
Definition at line 672 of file core_starmc1.h.
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
Definition at line 673 of file core_starmc1.h.
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
Definition at line 675 of file core_starmc1.h.
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
SCB CCR: DC Mask
Definition at line 676 of file core_starmc1.h.
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
Definition at line 678 of file core_starmc1.h.
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
Definition at line 679 of file core_starmc1.h.
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
Definition at line 681 of file core_starmc1.h.
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
Definition at line 682 of file core_starmc1.h.
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
Definition at line 684 of file core_starmc1.h.
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
Definition at line 685 of file core_starmc1.h.
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
Definition at line 687 of file core_starmc1.h.
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
Definition at line 688 of file core_starmc1.h.
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
Definition at line 690 of file core_starmc1.h.
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
Definition at line 691 of file core_starmc1.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
Definition at line 694 of file core_starmc1.h.
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
Definition at line 695 of file core_starmc1.h.
| #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
SCB SHCSR: SECUREFAULTPENDED Position
Definition at line 697 of file core_starmc1.h.
| #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
SCB SHCSR: SECUREFAULTPENDED Mask
Definition at line 698 of file core_starmc1.h.
| #define SCB_SHCSR_SECUREFAULTENA_Pos 19U |
SCB SHCSR: SECUREFAULTENA Position
Definition at line 700 of file core_starmc1.h.
| #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
SCB SHCSR: SECUREFAULTENA Mask
Definition at line 701 of file core_starmc1.h.
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
Definition at line 703 of file core_starmc1.h.
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
Definition at line 704 of file core_starmc1.h.
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
Definition at line 706 of file core_starmc1.h.
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
Definition at line 707 of file core_starmc1.h.
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
Definition at line 709 of file core_starmc1.h.
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
Definition at line 710 of file core_starmc1.h.
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
Definition at line 712 of file core_starmc1.h.
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
Definition at line 713 of file core_starmc1.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
Definition at line 715 of file core_starmc1.h.
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
Definition at line 716 of file core_starmc1.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
Definition at line 718 of file core_starmc1.h.
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
Definition at line 719 of file core_starmc1.h.
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
Definition at line 721 of file core_starmc1.h.
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
Definition at line 722 of file core_starmc1.h.
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
Definition at line 724 of file core_starmc1.h.
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
Definition at line 725 of file core_starmc1.h.
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
Definition at line 727 of file core_starmc1.h.
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
Definition at line 728 of file core_starmc1.h.
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
Definition at line 730 of file core_starmc1.h.
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
Definition at line 731 of file core_starmc1.h.
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
Definition at line 733 of file core_starmc1.h.
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
Definition at line 734 of file core_starmc1.h.
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
Definition at line 736 of file core_starmc1.h.
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
Definition at line 737 of file core_starmc1.h.
| #define SCB_SHCSR_SECUREFAULTACT_Pos 4U |
SCB SHCSR: SECUREFAULTACT Position
Definition at line 739 of file core_starmc1.h.
| #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
SCB SHCSR: SECUREFAULTACT Mask
Definition at line 740 of file core_starmc1.h.
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
Definition at line 742 of file core_starmc1.h.
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
Definition at line 743 of file core_starmc1.h.
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
Definition at line 745 of file core_starmc1.h.
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
Definition at line 746 of file core_starmc1.h.
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
Definition at line 748 of file core_starmc1.h.
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
Definition at line 749 of file core_starmc1.h.
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
Definition at line 751 of file core_starmc1.h.
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
Definition at line 752 of file core_starmc1.h.
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
Definition at line 755 of file core_starmc1.h.
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
Definition at line 756 of file core_starmc1.h.
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
Definition at line 758 of file core_starmc1.h.
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
Definition at line 759 of file core_starmc1.h.
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
Definition at line 761 of file core_starmc1.h.
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
Definition at line 762 of file core_starmc1.h.
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
Definition at line 765 of file core_starmc1.h.
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
Definition at line 766 of file core_starmc1.h.
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
Definition at line 768 of file core_starmc1.h.
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
Definition at line 769 of file core_starmc1.h.
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
Definition at line 771 of file core_starmc1.h.
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
Definition at line 772 of file core_starmc1.h.
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
Definition at line 774 of file core_starmc1.h.
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
Definition at line 775 of file core_starmc1.h.
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
Definition at line 777 of file core_starmc1.h.
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
Definition at line 778 of file core_starmc1.h.
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
Definition at line 780 of file core_starmc1.h.
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
Definition at line 781 of file core_starmc1.h.
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
Definition at line 784 of file core_starmc1.h.
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
Definition at line 785 of file core_starmc1.h.
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
Definition at line 787 of file core_starmc1.h.
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
Definition at line 788 of file core_starmc1.h.
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
Definition at line 790 of file core_starmc1.h.
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
Definition at line 791 of file core_starmc1.h.
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
Definition at line 793 of file core_starmc1.h.
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
Definition at line 794 of file core_starmc1.h.
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
Definition at line 796 of file core_starmc1.h.
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
Definition at line 797 of file core_starmc1.h.
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
Definition at line 799 of file core_starmc1.h.
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
Definition at line 800 of file core_starmc1.h.
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
Definition at line 802 of file core_starmc1.h.
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
Definition at line 803 of file core_starmc1.h.
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
Definition at line 806 of file core_starmc1.h.
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
Definition at line 807 of file core_starmc1.h.
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
Definition at line 809 of file core_starmc1.h.
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
Definition at line 810 of file core_starmc1.h.
| #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
SCB CFSR (UFSR): STKOF Position
Definition at line 812 of file core_starmc1.h.
| #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
SCB CFSR (UFSR): STKOF Mask
Definition at line 813 of file core_starmc1.h.
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
Definition at line 815 of file core_starmc1.h.
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
Definition at line 816 of file core_starmc1.h.
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
Definition at line 818 of file core_starmc1.h.
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
Definition at line 819 of file core_starmc1.h.
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
Definition at line 821 of file core_starmc1.h.
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
Definition at line 822 of file core_starmc1.h.
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
Definition at line 824 of file core_starmc1.h.
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
Definition at line 825 of file core_starmc1.h.
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
Definition at line 828 of file core_starmc1.h.
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
Definition at line 829 of file core_starmc1.h.
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
Definition at line 831 of file core_starmc1.h.
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
Definition at line 832 of file core_starmc1.h.
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
Definition at line 834 of file core_starmc1.h.
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
Definition at line 835 of file core_starmc1.h.
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
Definition at line 838 of file core_starmc1.h.
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
Definition at line 839 of file core_starmc1.h.
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
Definition at line 841 of file core_starmc1.h.
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
Definition at line 842 of file core_starmc1.h.
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
Definition at line 844 of file core_starmc1.h.
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
Definition at line 845 of file core_starmc1.h.
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
Definition at line 847 of file core_starmc1.h.
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
Definition at line 848 of file core_starmc1.h.
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
Definition at line 850 of file core_starmc1.h.
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
Definition at line 851 of file core_starmc1.h.
| #define SCB_NSACR_CP11_Pos 11U |
SCB NSACR: CP11 Position
Definition at line 854 of file core_starmc1.h.
| #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
SCB NSACR: CP11 Mask
Definition at line 855 of file core_starmc1.h.
| #define SCB_NSACR_CP10_Pos 10U |
SCB NSACR: CP10 Position
Definition at line 857 of file core_starmc1.h.
| #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
SCB NSACR: CP10 Mask
Definition at line 858 of file core_starmc1.h.
| #define SCB_NSACR_CPn_Pos 0U |
SCB NSACR: CPn Position
Definition at line 860 of file core_starmc1.h.
| #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) |
SCB NSACR: CPn Mask
Definition at line 861 of file core_starmc1.h.
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
Definition at line 864 of file core_starmc1.h.
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
Definition at line 865 of file core_starmc1.h.
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
Definition at line 867 of file core_starmc1.h.
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
Definition at line 868 of file core_starmc1.h.
| #define SCB_CLIDR_IC_Pos 0U |
SCB CLIDR: IC Position
Definition at line 870 of file core_starmc1.h.
| #define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) |
SCB CLIDR: IC Mask
Definition at line 871 of file core_starmc1.h.
| #define SCB_CLIDR_DC_Pos 1U |
SCB CLIDR: DC Position
Definition at line 873 of file core_starmc1.h.
| #define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) |
SCB CLIDR: DC Mask
Definition at line 874 of file core_starmc1.h.
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
Definition at line 879 of file core_starmc1.h.
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
Definition at line 880 of file core_starmc1.h.
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
Definition at line 882 of file core_starmc1.h.
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
Definition at line 883 of file core_starmc1.h.
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
Definition at line 885 of file core_starmc1.h.
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
Definition at line 886 of file core_starmc1.h.
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
Definition at line 888 of file core_starmc1.h.
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
Definition at line 889 of file core_starmc1.h.
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
Definition at line 891 of file core_starmc1.h.
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
Definition at line 892 of file core_starmc1.h.
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
Definition at line 895 of file core_starmc1.h.
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
Definition at line 896 of file core_starmc1.h.
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
Definition at line 898 of file core_starmc1.h.
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
Definition at line 899 of file core_starmc1.h.
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
Definition at line 901 of file core_starmc1.h.
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
Definition at line 902 of file core_starmc1.h.
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
Definition at line 904 of file core_starmc1.h.
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
Definition at line 905 of file core_starmc1.h.
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
Definition at line 907 of file core_starmc1.h.
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
Definition at line 908 of file core_starmc1.h.
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
Definition at line 910 of file core_starmc1.h.
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
Definition at line 911 of file core_starmc1.h.
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
Definition at line 913 of file core_starmc1.h.
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
Definition at line 914 of file core_starmc1.h.
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
Definition at line 917 of file core_starmc1.h.
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
Definition at line 918 of file core_starmc1.h.
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
Definition at line 920 of file core_starmc1.h.
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
Definition at line 921 of file core_starmc1.h.
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
Definition at line 924 of file core_starmc1.h.
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
Definition at line 925 of file core_starmc1.h.
| #define SCB_DCISW_LEVEL_Pos 1U |
SCB DCISW: Level Position
Definition at line 928 of file core_starmc1.h.
| #define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) |
SCB DCISW: Level Mask
Definition at line 929 of file core_starmc1.h.
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
Definition at line 931 of file core_starmc1.h.
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
Definition at line 932 of file core_starmc1.h.
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
Definition at line 934 of file core_starmc1.h.
| #define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
Definition at line 935 of file core_starmc1.h.
| #define SCB_DCCSW_LEVEL_Pos 1U |
SCB DCCSW: Level Position
Definition at line 938 of file core_starmc1.h.
| #define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) |
SCB DCCSW: Level Mask
Definition at line 939 of file core_starmc1.h.
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
Definition at line 941 of file core_starmc1.h.
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
Definition at line 942 of file core_starmc1.h.
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
Definition at line 944 of file core_starmc1.h.
| #define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
Definition at line 945 of file core_starmc1.h.
| #define SCB_DCCISW_LEVEL_Pos 1U |
SCB DCCISW: Level Position
Definition at line 948 of file core_starmc1.h.
| #define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) |
SCB DCCISW: Level Mask
Definition at line 949 of file core_starmc1.h.
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
Definition at line 951 of file core_starmc1.h.
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
Definition at line 952 of file core_starmc1.h.
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
Definition at line 954 of file core_starmc1.h.
| #define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
Definition at line 955 of file core_starmc1.h.
| #define SCB_ITCMCR_SZ_Pos 3U |
SCB ITCMCR: SZ Position
Definition at line 959 of file core_starmc1.h.
| #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) |
SCB ITCMCR: SZ Mask
Definition at line 960 of file core_starmc1.h.
| #define SCB_ITCMCR_EN_Pos 0U |
SCB ITCMCR: EN Position
Definition at line 962 of file core_starmc1.h.
| #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) |
SCB ITCMCR: EN Mask
Definition at line 963 of file core_starmc1.h.
| #define SCB_DTCMCR_SZ_Pos 3U |
SCB DTCMCR: SZ Position
Definition at line 966 of file core_starmc1.h.
| #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) |
SCB DTCMCR: SZ Mask
Definition at line 967 of file core_starmc1.h.
| #define SCB_DTCMCR_EN_Pos 0U |
SCB DTCMCR: EN Position
Definition at line 969 of file core_starmc1.h.
| #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) |
SCB DTCMCR: EN Mask
Definition at line 970 of file core_starmc1.h.
| #define SCB_CACR_DCCLEAN_Pos 16U |
SCB CACR: DCCLEAN Position
Definition at line 973 of file core_starmc1.h.
| #define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
SCB CACR: DCCLEAN Mask
Definition at line 974 of file core_starmc1.h.
| #define SCB_CACR_ICACTIVE_Pos 13U |
SCB CACR: ICACTIVE Position
Definition at line 976 of file core_starmc1.h.
| #define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
SCB CACR: ICACTIVE Mask
Definition at line 977 of file core_starmc1.h.
| #define SCB_CACR_DCACTIVE_Pos 12U |
SCB CACR: DCACTIVE Position
Definition at line 979 of file core_starmc1.h.
| #define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
SCB CACR: DCACTIVE Mask
Definition at line 980 of file core_starmc1.h.
| #define SCB_CACR_FORCEWT_Pos 2U |
SCB CACR: FORCEWT Position
Definition at line 982 of file core_starmc1.h.
| #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
SCB CACR: FORCEWT Mask
Definition at line 983 of file core_starmc1.h.
| #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U |
ACTLR: DISMCYCINT Position
Definition at line 472 of file core_sc000.h.
| #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) |
ACTLR: DISMCYCINT Mask
Definition at line 473 of file core_sc000.h.
| #define SCnSCB_ACTLR_DISFOLD_Pos 2U |
ACTLR: DISFOLD Position
Definition at line 669 of file core_sc300.h.
| #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) |
ACTLR: DISFOLD Mask
Definition at line 670 of file core_sc300.h.
| #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U |
ACTLR: DISDEFWBUF Position
Definition at line 672 of file core_sc300.h.
| #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) |
ACTLR: DISDEFWBUF Mask
Definition at line 673 of file core_sc300.h.
| #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U |
ACTLR: DISMCYCINT Position
Definition at line 675 of file core_sc300.h.
| #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) |
ACTLR: DISMCYCINT Mask
Definition at line 676 of file core_sc300.h.
| #define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
Definition at line 1007 of file core_starmc1.h.
| #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
Definition at line 1008 of file core_starmc1.h.
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
Definition at line 1032 of file core_starmc1.h.
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
Definition at line 1033 of file core_starmc1.h.
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
Definition at line 1035 of file core_starmc1.h.
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
Definition at line 1036 of file core_starmc1.h.
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
Definition at line 1038 of file core_starmc1.h.
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
Definition at line 1039 of file core_starmc1.h.
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
Definition at line 1041 of file core_starmc1.h.
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
Definition at line 1042 of file core_starmc1.h.
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
Definition at line 1045 of file core_starmc1.h.
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
Definition at line 1046 of file core_starmc1.h.
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
Definition at line 1049 of file core_starmc1.h.
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
Definition at line 1050 of file core_starmc1.h.
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
Definition at line 1053 of file core_starmc1.h.
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
Definition at line 1054 of file core_starmc1.h.
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
Definition at line 1056 of file core_starmc1.h.
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
Definition at line 1057 of file core_starmc1.h.
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
Definition at line 1059 of file core_starmc1.h.
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
Definition at line 1060 of file core_starmc1.h.
| #define ITM_TCR_TraceBusID_Pos 16U |
ITM TCR: ATBID Position
Definition at line 784 of file core_sc300.h.
| #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) |
ITM TCR: ATBID Mask
Definition at line 785 of file core_sc300.h.
| #define ITM_TCR_TSPrescale_Pos 8U |
ITM TCR: TSPrescale Position
Definition at line 790 of file core_sc300.h.
| #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) |
ITM TCR: TSPrescale Mask
Definition at line 791 of file core_sc300.h.
| #define ITM_STIM_DISABLED_Pos 1U |
ITM STIM: DISABLED Position
Definition at line 1111 of file core_starmc1.h.
| #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) |
ITM STIM: DISABLED Mask
Definition at line 1112 of file core_starmc1.h.
| #define ITM_STIM_FIFOREADY_Pos 0U |
ITM STIM: FIFOREADY Position
Definition at line 1114 of file core_starmc1.h.
| #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) |
ITM STIM: FIFOREADY Mask
Definition at line 1115 of file core_starmc1.h.
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
Definition at line 1118 of file core_starmc1.h.
| #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
Definition at line 1119 of file core_starmc1.h.
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
Definition at line 1122 of file core_starmc1.h.
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
Definition at line 1123 of file core_starmc1.h.
| #define ITM_TCR_TRACEBUSID_Pos 16U |
ITM TCR: ATBID Position
Definition at line 1125 of file core_starmc1.h.
| #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) |
ITM TCR: ATBID Mask
Definition at line 1126 of file core_starmc1.h.
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
Definition at line 1128 of file core_starmc1.h.
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
Definition at line 1129 of file core_starmc1.h.
| #define ITM_TCR_TSPRESCALE_Pos 8U |
ITM TCR: TSPRESCALE Position
Definition at line 1131 of file core_starmc1.h.
| #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) |
ITM TCR: TSPRESCALE Mask
Definition at line 1132 of file core_starmc1.h.
| #define ITM_TCR_STALLENA_Pos 5U |
ITM TCR: STALLENA Position
Definition at line 1134 of file core_starmc1.h.
| #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) |
ITM TCR: STALLENA Mask
Definition at line 1135 of file core_starmc1.h.
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
Definition at line 1137 of file core_starmc1.h.
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
Definition at line 1138 of file core_starmc1.h.
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
Definition at line 1140 of file core_starmc1.h.
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
Definition at line 1141 of file core_starmc1.h.
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
Definition at line 1143 of file core_starmc1.h.
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
Definition at line 1144 of file core_starmc1.h.
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
Definition at line 1146 of file core_starmc1.h.
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
Definition at line 1147 of file core_starmc1.h.
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
Definition at line 1149 of file core_starmc1.h.
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
Definition at line 1150 of file core_starmc1.h.
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
Definition at line 1153 of file core_starmc1.h.
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
Definition at line 1154 of file core_starmc1.h.
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
Definition at line 1156 of file core_starmc1.h.
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
Definition at line 1157 of file core_starmc1.h.
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
Definition at line 1159 of file core_starmc1.h.
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
Definition at line 1160 of file core_starmc1.h.
| #define DWT_MASK_MASK_Pos 0U |
DWT MASK: MASK Position
Definition at line 934 of file core_sc300.h.
| #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) |
DWT MASK: MASK Mask
Definition at line 935 of file core_sc300.h.
| #define DWT_FUNCTION_DATAVADDR1_Pos 16U |
DWT FUNCTION: DATAVADDR1 Position
Definition at line 941 of file core_sc300.h.
| #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) |
DWT FUNCTION: DATAVADDR1 Mask
Definition at line 942 of file core_sc300.h.
| #define DWT_FUNCTION_DATAVADDR0_Pos 12U |
DWT FUNCTION: DATAVADDR0 Position
Definition at line 944 of file core_sc300.h.
| #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) |
DWT FUNCTION: DATAVADDR0 Mask
Definition at line 945 of file core_sc300.h.
| #define DWT_FUNCTION_LNK1ENA_Pos 9U |
DWT FUNCTION: LNK1ENA Position
Definition at line 950 of file core_sc300.h.
| #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) |
DWT FUNCTION: LNK1ENA Mask
Definition at line 951 of file core_sc300.h.
| #define DWT_FUNCTION_DATAVMATCH_Pos 8U |
DWT FUNCTION: DATAVMATCH Position
Definition at line 953 of file core_sc300.h.
| #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) |
DWT FUNCTION: DATAVMATCH Mask
Definition at line 954 of file core_sc300.h.
| #define DWT_FUNCTION_CYCMATCH_Pos 7U |
DWT FUNCTION: CYCMATCH Position
Definition at line 956 of file core_sc300.h.
| #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) |
DWT FUNCTION: CYCMATCH Mask
Definition at line 957 of file core_sc300.h.
| #define DWT_FUNCTION_EMITRANGE_Pos 5U |
DWT FUNCTION: EMITRANGE Position
Definition at line 959 of file core_sc300.h.
| #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) |
DWT FUNCTION: EMITRANGE Mask
Definition at line 960 of file core_sc300.h.
| #define DWT_FUNCTION_FUNCTION_Pos 0U |
DWT FUNCTION: FUNCTION Position
Definition at line 962 of file core_sc300.h.
| #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) |
DWT FUNCTION: FUNCTION Mask
Definition at line 963 of file core_sc300.h.
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
Definition at line 1255 of file core_starmc1.h.
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
Definition at line 1256 of file core_starmc1.h.
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
Definition at line 1258 of file core_starmc1.h.
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
Definition at line 1259 of file core_starmc1.h.
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
Definition at line 1261 of file core_starmc1.h.
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
Definition at line 1262 of file core_starmc1.h.
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
Definition at line 1264 of file core_starmc1.h.
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
Definition at line 1265 of file core_starmc1.h.
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
Definition at line 1267 of file core_starmc1.h.
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
Definition at line 1268 of file core_starmc1.h.
| #define DWT_CTRL_CYCDISS_Pos 23U |
DWT CTRL: CYCDISS Position
Definition at line 1270 of file core_starmc1.h.
| #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) |
DWT CTRL: CYCDISS Mask
Definition at line 1271 of file core_starmc1.h.
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
Definition at line 1273 of file core_starmc1.h.
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
Definition at line 1274 of file core_starmc1.h.
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
Definition at line 1276 of file core_starmc1.h.
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
Definition at line 1277 of file core_starmc1.h.
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
Definition at line 1279 of file core_starmc1.h.
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
Definition at line 1280 of file core_starmc1.h.
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
Definition at line 1282 of file core_starmc1.h.
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
Definition at line 1283 of file core_starmc1.h.
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
Definition at line 1285 of file core_starmc1.h.
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
Definition at line 1286 of file core_starmc1.h.
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
Definition at line 1288 of file core_starmc1.h.
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
Definition at line 1289 of file core_starmc1.h.
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
Definition at line 1291 of file core_starmc1.h.
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
Definition at line 1292 of file core_starmc1.h.
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
Definition at line 1294 of file core_starmc1.h.
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
Definition at line 1295 of file core_starmc1.h.
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
Definition at line 1297 of file core_starmc1.h.
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
Definition at line 1298 of file core_starmc1.h.
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
Definition at line 1300 of file core_starmc1.h.
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
Definition at line 1301 of file core_starmc1.h.
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
Definition at line 1303 of file core_starmc1.h.
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
Definition at line 1304 of file core_starmc1.h.
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
Definition at line 1306 of file core_starmc1.h.
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
Definition at line 1307 of file core_starmc1.h.
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
Definition at line 1309 of file core_starmc1.h.
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
Definition at line 1310 of file core_starmc1.h.
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
Definition at line 1313 of file core_starmc1.h.
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
Definition at line 1314 of file core_starmc1.h.
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
Definition at line 1317 of file core_starmc1.h.
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
Definition at line 1318 of file core_starmc1.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
Definition at line 1321 of file core_starmc1.h.
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
Definition at line 1322 of file core_starmc1.h.
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
Definition at line 1325 of file core_starmc1.h.
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
Definition at line 1326 of file core_starmc1.h.
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
Definition at line 1329 of file core_starmc1.h.
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
Definition at line 1330 of file core_starmc1.h.
| #define DWT_FUNCTION_ID_Pos 27U |
DWT FUNCTION: ID Position
Definition at line 1333 of file core_starmc1.h.
| #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) |
DWT FUNCTION: ID Mask
Definition at line 1334 of file core_starmc1.h.
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
Definition at line 1336 of file core_starmc1.h.
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
Definition at line 1337 of file core_starmc1.h.
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
Definition at line 1339 of file core_starmc1.h.
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
Definition at line 1340 of file core_starmc1.h.
| #define DWT_FUNCTION_ACTION_Pos 4U |
DWT FUNCTION: ACTION Position
Definition at line 1342 of file core_starmc1.h.
| #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) |
DWT FUNCTION: ACTION Mask
Definition at line 1343 of file core_starmc1.h.
| #define DWT_FUNCTION_MATCH_Pos 0U |
DWT FUNCTION: MATCH Position
Definition at line 1345 of file core_starmc1.h.
| #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) |
DWT FUNCTION: MATCH Mask
Definition at line 1346 of file core_starmc1.h.
| #define TPI_FIFO0_ITM_ATVALID_Pos 29U |
TPI FIFO0: ITM_ATVALID Position
Definition at line 1039 of file core_sc300.h.
| #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
Definition at line 1040 of file core_sc300.h.
| #define TPI_FIFO0_ITM_bytecount_Pos 27U |
TPI FIFO0: ITM_bytecount Position
Definition at line 1042 of file core_sc300.h.
| #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
Definition at line 1043 of file core_sc300.h.
| #define TPI_FIFO0_ETM_ATVALID_Pos 26U |
TPI FIFO0: ETM_ATVALID Position
Definition at line 1045 of file core_sc300.h.
| #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
Definition at line 1046 of file core_sc300.h.
| #define TPI_FIFO0_ETM_bytecount_Pos 24U |
TPI FIFO0: ETM_bytecount Position
Definition at line 1048 of file core_sc300.h.
| #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
Definition at line 1049 of file core_sc300.h.
| #define TPI_FIFO0_ETM2_Pos 16U |
TPI FIFO0: ETM2 Position
Definition at line 1051 of file core_sc300.h.
| #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
Definition at line 1052 of file core_sc300.h.
| #define TPI_FIFO0_ETM1_Pos 8U |
TPI FIFO0: ETM1 Position
Definition at line 1054 of file core_sc300.h.
| #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
Definition at line 1055 of file core_sc300.h.
| #define TPI_FIFO0_ETM0_Pos 0U |
TPI FIFO0: ETM0 Position
Definition at line 1057 of file core_sc300.h.
| #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
TPI FIFO0: ETM0 Mask
Definition at line 1058 of file core_sc300.h.
| #define TPI_ITATBCTR2_ATREADY2_Pos 0U |
TPI ITATBCTR2: ATREADY2 Position
Definition at line 1061 of file core_sc300.h.
| #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) |
TPI ITATBCTR2: ATREADY2 Mask
Definition at line 1062 of file core_sc300.h.
| #define TPI_ITATBCTR2_ATREADY1_Pos 0U |
TPI ITATBCTR2: ATREADY1 Position
Definition at line 1064 of file core_sc300.h.
| #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) |
TPI ITATBCTR2: ATREADY1 Mask
Definition at line 1065 of file core_sc300.h.
| #define TPI_FIFO1_ITM_ATVALID_Pos 29U |
TPI FIFO1: ITM_ATVALID Position
Definition at line 1068 of file core_sc300.h.
| #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
Definition at line 1069 of file core_sc300.h.
| #define TPI_FIFO1_ITM_bytecount_Pos 27U |
TPI FIFO1: ITM_bytecount Position
Definition at line 1071 of file core_sc300.h.
| #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
Definition at line 1072 of file core_sc300.h.
| #define TPI_FIFO1_ETM_ATVALID_Pos 26U |
TPI FIFO1: ETM_ATVALID Position
Definition at line 1074 of file core_sc300.h.
| #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
Definition at line 1075 of file core_sc300.h.
| #define TPI_FIFO1_ETM_bytecount_Pos 24U |
TPI FIFO1: ETM_bytecount Position
Definition at line 1077 of file core_sc300.h.
| #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
Definition at line 1078 of file core_sc300.h.
| #define TPI_FIFO1_ITM2_Pos 16U |
TPI FIFO1: ITM2 Position
Definition at line 1080 of file core_sc300.h.
| #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
Definition at line 1081 of file core_sc300.h.
| #define TPI_FIFO1_ITM1_Pos 8U |
TPI FIFO1: ITM1 Position
Definition at line 1083 of file core_sc300.h.
| #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
Definition at line 1084 of file core_sc300.h.
| #define TPI_FIFO1_ITM0_Pos 0U |
TPI FIFO1: ITM0 Position
Definition at line 1086 of file core_sc300.h.
| #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
TPI FIFO1: ITM0 Mask
Definition at line 1087 of file core_sc300.h.
| #define TPI_ITATBCTR0_ATREADY2_Pos 0U |
TPI ITATBCTR0: ATREADY2 Position
Definition at line 1090 of file core_sc300.h.
| #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) |
TPI ITATBCTR0: ATREADY2 Mask
Definition at line 1091 of file core_sc300.h.
| #define TPI_ITATBCTR0_ATREADY1_Pos 0U |
TPI ITATBCTR0: ATREADY1 Position
Definition at line 1093 of file core_sc300.h.
| #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) |
TPI ITATBCTR0: ATREADY1 Mask
Definition at line 1094 of file core_sc300.h.
| #define TPI_DEVID_MinBufSz_Pos 6U |
TPI DEVID: MinBufSz Position
Definition at line 1110 of file core_sc300.h.
| #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
Definition at line 1111 of file core_sc300.h.
| #define TPI_DEVID_AsynClkIn_Pos 5U |
TPI DEVID: AsynClkIn Position
Definition at line 1113 of file core_sc300.h.
| #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
Definition at line 1114 of file core_sc300.h.
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
Definition at line 1390 of file core_starmc1.h.
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
Definition at line 1391 of file core_starmc1.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 1394 of file core_starmc1.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 1395 of file core_starmc1.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 1398 of file core_starmc1.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 1399 of file core_starmc1.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 1401 of file core_starmc1.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 1402 of file core_starmc1.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 1404 of file core_starmc1.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 1405 of file core_starmc1.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 1407 of file core_starmc1.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 1408 of file core_starmc1.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 1411 of file core_starmc1.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 1412 of file core_starmc1.h.
| #define TPI_FFCR_FOnMan_Pos 6U |
TPI FFCR: FOnMan Position
Definition at line 1414 of file core_starmc1.h.
| #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) |
TPI FFCR: FOnMan Mask
Definition at line 1415 of file core_starmc1.h.
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
Definition at line 1417 of file core_starmc1.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 1418 of file core_starmc1.h.
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
Definition at line 1421 of file core_starmc1.h.
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
Definition at line 1422 of file core_starmc1.h.
| #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U |
TPI ITFTTD0: ATB Interface 2 ATVALIDPosition
Definition at line 1425 of file core_starmc1.h.
| #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) |
TPI ITFTTD0: ATB Interface 2 ATVALID Mask
Definition at line 1426 of file core_starmc1.h.
| #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U |
TPI ITFTTD0: ATB Interface 2 byte count Position
Definition at line 1428 of file core_starmc1.h.
| #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) |
TPI ITFTTD0: ATB Interface 2 byte count Mask
Definition at line 1429 of file core_starmc1.h.
| #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U |
TPI ITFTTD0: ATB Interface 1 ATVALID Position
Definition at line 1431 of file core_starmc1.h.
| #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) |
TPI ITFTTD0: ATB Interface 1 ATVALID Mask
Definition at line 1432 of file core_starmc1.h.
| #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U |
TPI ITFTTD0: ATB Interface 1 byte count Position
Definition at line 1434 of file core_starmc1.h.
| #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) |
TPI ITFTTD0: ATB Interface 1 byte countt Mask
Definition at line 1435 of file core_starmc1.h.
| #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U |
TPI ITFTTD0: ATB Interface 1 data2 Position
Definition at line 1437 of file core_starmc1.h.
| #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) |
TPI ITFTTD0: ATB Interface 1 data2 Mask
Definition at line 1438 of file core_starmc1.h.
| #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U |
TPI ITFTTD0: ATB Interface 1 data1 Position
Definition at line 1440 of file core_starmc1.h.
| #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) |
TPI ITFTTD0: ATB Interface 1 data1 Mask
Definition at line 1441 of file core_starmc1.h.
| #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U |
TPI ITFTTD0: ATB Interface 1 data0 Position
Definition at line 1443 of file core_starmc1.h.
| #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) |
TPI ITFTTD0: ATB Interface 1 data0 Mask
Definition at line 1444 of file core_starmc1.h.
| #define TPI_ITATBCTR2_AFVALID2S_Pos 1U |
TPI ITATBCTR2: AFVALID2S Position
Definition at line 1447 of file core_starmc1.h.
| #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) |
TPI ITATBCTR2: AFVALID2SS Mask
Definition at line 1448 of file core_starmc1.h.
| #define TPI_ITATBCTR2_AFVALID1S_Pos 1U |
TPI ITATBCTR2: AFVALID1S Position
Definition at line 1450 of file core_starmc1.h.
| #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) |
TPI ITATBCTR2: AFVALID1SS Mask
Definition at line 1451 of file core_starmc1.h.
| #define TPI_ITATBCTR2_ATREADY2S_Pos 0U |
TPI ITATBCTR2: ATREADY2S Position
Definition at line 1453 of file core_starmc1.h.
| #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) |
TPI ITATBCTR2: ATREADY2S Mask
Definition at line 1454 of file core_starmc1.h.
| #define TPI_ITATBCTR2_ATREADY1S_Pos 0U |
TPI ITATBCTR2: ATREADY1S Position
Definition at line 1456 of file core_starmc1.h.
| #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) |
TPI ITATBCTR2: ATREADY1S Mask
Definition at line 1457 of file core_starmc1.h.
| #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U |
TPI ITFTTD1: ATB Interface 2 ATVALID Position
Definition at line 1460 of file core_starmc1.h.
| #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) |
TPI ITFTTD1: ATB Interface 2 ATVALID Mask
Definition at line 1461 of file core_starmc1.h.
| #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U |
TPI ITFTTD1: ATB Interface 2 byte count Position
Definition at line 1463 of file core_starmc1.h.
| #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) |
TPI ITFTTD1: ATB Interface 2 byte count Mask
Definition at line 1464 of file core_starmc1.h.
| #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U |
TPI ITFTTD1: ATB Interface 1 ATVALID Position
Definition at line 1466 of file core_starmc1.h.
| #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) |
TPI ITFTTD1: ATB Interface 1 ATVALID Mask
Definition at line 1467 of file core_starmc1.h.
| #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U |
TPI ITFTTD1: ATB Interface 1 byte count Position
Definition at line 1469 of file core_starmc1.h.
| #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) |
TPI ITFTTD1: ATB Interface 1 byte countt Mask
Definition at line 1470 of file core_starmc1.h.
| #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U |
TPI ITFTTD1: ATB Interface 2 data2 Position
Definition at line 1472 of file core_starmc1.h.
| #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) |
TPI ITFTTD1: ATB Interface 2 data2 Mask
Definition at line 1473 of file core_starmc1.h.
| #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U |
TPI ITFTTD1: ATB Interface 2 data1 Position
Definition at line 1475 of file core_starmc1.h.
| #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) |
TPI ITFTTD1: ATB Interface 2 data1 Mask
Definition at line 1476 of file core_starmc1.h.
| #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U |
TPI ITFTTD1: ATB Interface 2 data0 Position
Definition at line 1478 of file core_starmc1.h.
| #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) |
TPI ITFTTD1: ATB Interface 2 data0 Mask
Definition at line 1479 of file core_starmc1.h.
| #define TPI_ITATBCTR0_AFVALID2S_Pos 1U |
TPI ITATBCTR0: AFVALID2S Position
Definition at line 1482 of file core_starmc1.h.
| #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) |
TPI ITATBCTR0: AFVALID2SS Mask
Definition at line 1483 of file core_starmc1.h.
| #define TPI_ITATBCTR0_AFVALID1S_Pos 1U |
TPI ITATBCTR0: AFVALID1S Position
Definition at line 1485 of file core_starmc1.h.
| #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) |
TPI ITATBCTR0: AFVALID1SS Mask
Definition at line 1486 of file core_starmc1.h.
| #define TPI_ITATBCTR0_ATREADY2S_Pos 0U |
TPI ITATBCTR0: ATREADY2S Position
Definition at line 1488 of file core_starmc1.h.
| #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) |
TPI ITATBCTR0: ATREADY2S Mask
Definition at line 1489 of file core_starmc1.h.
| #define TPI_ITATBCTR0_ATREADY1S_Pos 0U |
TPI ITATBCTR0: ATREADY1S Position
Definition at line 1491 of file core_starmc1.h.
| #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) |
TPI ITATBCTR0: ATREADY1S Mask
Definition at line 1492 of file core_starmc1.h.
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
Definition at line 1495 of file core_starmc1.h.
| #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
Definition at line 1496 of file core_starmc1.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 1499 of file core_starmc1.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1500 of file core_starmc1.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 1502 of file core_starmc1.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1503 of file core_starmc1.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 1505 of file core_starmc1.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1506 of file core_starmc1.h.
| #define TPI_DEVID_FIFOSZ_Pos 6U |
TPI DEVID: FIFOSZ Position
Definition at line 1508 of file core_starmc1.h.
| #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) |
TPI DEVID: FIFOSZ Mask
Definition at line 1509 of file core_starmc1.h.
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
Definition at line 1511 of file core_starmc1.h.
| #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
Definition at line 1512 of file core_starmc1.h.
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
Definition at line 1515 of file core_starmc1.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 1516 of file core_starmc1.h.
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
Definition at line 1518 of file core_starmc1.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1519 of file core_starmc1.h.
| #define MPU_TYPE_IREGION_Pos 16U |
MPU TYPE: IREGION Position
Definition at line 1561 of file core_starmc1.h.
| #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) |
MPU TYPE: IREGION Mask
Definition at line 1562 of file core_starmc1.h.
| #define MPU_TYPE_DREGION_Pos 8U |
MPU TYPE: DREGION Position
Definition at line 1564 of file core_starmc1.h.
| #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) |
MPU TYPE: DREGION Mask
Definition at line 1565 of file core_starmc1.h.
| #define MPU_TYPE_SEPARATE_Pos 0U |
MPU TYPE: SEPARATE Position
Definition at line 1567 of file core_starmc1.h.
| #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) |
MPU TYPE: SEPARATE Mask
Definition at line 1568 of file core_starmc1.h.
| #define MPU_CTRL_PRIVDEFENA_Pos 2U |
MPU CTRL: PRIVDEFENA Position
Definition at line 1571 of file core_starmc1.h.
| #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) |
MPU CTRL: PRIVDEFENA Mask
Definition at line 1572 of file core_starmc1.h.
| #define MPU_CTRL_HFNMIENA_Pos 1U |
MPU CTRL: HFNMIENA Position
Definition at line 1574 of file core_starmc1.h.
| #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) |
MPU CTRL: HFNMIENA Mask
Definition at line 1575 of file core_starmc1.h.
| #define MPU_CTRL_ENABLE_Pos 0U |
MPU CTRL: ENABLE Position
Definition at line 1577 of file core_starmc1.h.
| #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) |
MPU CTRL: ENABLE Mask
Definition at line 1578 of file core_starmc1.h.
| #define MPU_RNR_REGION_Pos 0U |
MPU RNR: REGION Position
Definition at line 1581 of file core_starmc1.h.
| #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) |
MPU RNR: REGION Mask
Definition at line 1582 of file core_starmc1.h.
| #define MPU_RBAR_BASE_Pos 5U |
MPU RBAR: BASE Position
Definition at line 1585 of file core_starmc1.h.
| #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) |
MPU RBAR: BASE Mask
Definition at line 1586 of file core_starmc1.h.
| #define MPU_RBAR_SH_Pos 3U |
MPU RBAR: SH Position
Definition at line 1588 of file core_starmc1.h.
| #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) |
MPU RBAR: SH Mask
Definition at line 1589 of file core_starmc1.h.
| #define MPU_RBAR_AP_Pos 1U |
MPU RBAR: AP Position
Definition at line 1591 of file core_starmc1.h.
| #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) |
MPU RBAR: AP Mask
Definition at line 1592 of file core_starmc1.h.
| #define MPU_RBAR_XN_Pos 0U |
MPU RBAR: XN Position
Definition at line 1594 of file core_starmc1.h.
| #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) |
MPU RBAR: XN Mask
Definition at line 1595 of file core_starmc1.h.
| #define MPU_RLAR_LIMIT_Pos 5U |
MPU RLAR: LIMIT Position
Definition at line 1598 of file core_starmc1.h.
| #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) |
MPU RLAR: LIMIT Mask
Definition at line 1599 of file core_starmc1.h.
| #define MPU_RLAR_AttrIndx_Pos 1U |
MPU RLAR: AttrIndx Position
Definition at line 1601 of file core_starmc1.h.
| #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) |
MPU RLAR: AttrIndx Mask
Definition at line 1602 of file core_starmc1.h.
| #define MPU_RLAR_EN_Pos 0U |
MPU RLAR: Region enable bit Position
Definition at line 1604 of file core_starmc1.h.
| #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) |
MPU RLAR: Region enable bit Disable Mask
Definition at line 1605 of file core_starmc1.h.
| #define MPU_MAIR0_Attr3_Pos 24U |
MPU MAIR0: Attr3 Position
Definition at line 1608 of file core_starmc1.h.
| #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) |
MPU MAIR0: Attr3 Mask
Definition at line 1609 of file core_starmc1.h.
| #define MPU_MAIR0_Attr2_Pos 16U |
MPU MAIR0: Attr2 Position
Definition at line 1611 of file core_starmc1.h.
| #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) |
MPU MAIR0: Attr2 Mask
Definition at line 1612 of file core_starmc1.h.
| #define MPU_MAIR0_Attr1_Pos 8U |
MPU MAIR0: Attr1 Position
Definition at line 1614 of file core_starmc1.h.
| #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) |
MPU MAIR0: Attr1 Mask
Definition at line 1615 of file core_starmc1.h.
| #define MPU_MAIR0_Attr0_Pos 0U |
MPU MAIR0: Attr0 Position
Definition at line 1617 of file core_starmc1.h.
| #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) |
MPU MAIR0: Attr0 Mask
Definition at line 1618 of file core_starmc1.h.
| #define MPU_MAIR1_Attr7_Pos 24U |
MPU MAIR1: Attr7 Position
Definition at line 1621 of file core_starmc1.h.
| #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) |
MPU MAIR1: Attr7 Mask
Definition at line 1622 of file core_starmc1.h.
| #define MPU_MAIR1_Attr6_Pos 16U |
MPU MAIR1: Attr6 Position
Definition at line 1624 of file core_starmc1.h.
| #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) |
MPU MAIR1: Attr6 Mask
Definition at line 1625 of file core_starmc1.h.
| #define MPU_MAIR1_Attr5_Pos 8U |
MPU MAIR1: Attr5 Position
Definition at line 1627 of file core_starmc1.h.
| #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) |
MPU MAIR1: Attr5 Mask
Definition at line 1628 of file core_starmc1.h.
| #define MPU_MAIR1_Attr4_Pos 0U |
MPU MAIR1: Attr4 Position
Definition at line 1630 of file core_starmc1.h.
| #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) |
MPU MAIR1: Attr4 Mask
Definition at line 1631 of file core_starmc1.h.
| #define FPU_FPCCR_ASPEN_Pos 31U |
FPCCR: ASPEN bit Position
Definition at line 1746 of file core_starmc1.h.
| #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) |
FPCCR: ASPEN bit Mask
Definition at line 1747 of file core_starmc1.h.
| #define FPU_FPCCR_LSPEN_Pos 30U |
FPCCR: LSPEN Position
Definition at line 1749 of file core_starmc1.h.
| #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) |
FPCCR: LSPEN bit Mask
Definition at line 1750 of file core_starmc1.h.
| #define FPU_FPCCR_LSPENS_Pos 29U |
FPCCR: LSPENS Position
Definition at line 1752 of file core_starmc1.h.
| #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) |
FPCCR: LSPENS bit Mask
Definition at line 1753 of file core_starmc1.h.
| #define FPU_FPCCR_CLRONRET_Pos 28U |
FPCCR: CLRONRET Position
Definition at line 1755 of file core_starmc1.h.
| #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) |
FPCCR: CLRONRET bit Mask
Definition at line 1756 of file core_starmc1.h.
| #define FPU_FPCCR_CLRONRETS_Pos 27U |
FPCCR: CLRONRETS Position
Definition at line 1758 of file core_starmc1.h.
| #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) |
FPCCR: CLRONRETS bit Mask
Definition at line 1759 of file core_starmc1.h.
| #define FPU_FPCCR_TS_Pos 26U |
FPCCR: TS Position
Definition at line 1761 of file core_starmc1.h.
| #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) |
FPCCR: TS bit Mask
Definition at line 1762 of file core_starmc1.h.
| #define FPU_FPCCR_UFRDY_Pos 10U |
FPCCR: UFRDY Position
Definition at line 1764 of file core_starmc1.h.
| #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) |
FPCCR: UFRDY bit Mask
Definition at line 1765 of file core_starmc1.h.
| #define FPU_FPCCR_SPLIMVIOL_Pos 9U |
FPCCR: SPLIMVIOL Position
Definition at line 1767 of file core_starmc1.h.
| #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) |
FPCCR: SPLIMVIOL bit Mask
Definition at line 1768 of file core_starmc1.h.
| #define FPU_FPCCR_MONRDY_Pos 8U |
FPCCR: MONRDY Position
Definition at line 1770 of file core_starmc1.h.
| #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) |
FPCCR: MONRDY bit Mask
Definition at line 1771 of file core_starmc1.h.
| #define FPU_FPCCR_SFRDY_Pos 7U |
FPCCR: SFRDY Position
Definition at line 1773 of file core_starmc1.h.
| #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) |
FPCCR: SFRDY bit Mask
Definition at line 1774 of file core_starmc1.h.
| #define FPU_FPCCR_BFRDY_Pos 6U |
FPCCR: BFRDY Position
Definition at line 1776 of file core_starmc1.h.
| #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) |
FPCCR: BFRDY bit Mask
Definition at line 1777 of file core_starmc1.h.
| #define FPU_FPCCR_MMRDY_Pos 5U |
FPCCR: MMRDY Position
Definition at line 1779 of file core_starmc1.h.
| #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) |
FPCCR: MMRDY bit Mask
Definition at line 1780 of file core_starmc1.h.
| #define FPU_FPCCR_HFRDY_Pos 4U |
FPCCR: HFRDY Position
Definition at line 1782 of file core_starmc1.h.
| #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) |
FPCCR: HFRDY bit Mask
Definition at line 1783 of file core_starmc1.h.
| #define FPU_FPCCR_THREAD_Pos 3U |
FPCCR: processor mode bit Position
Definition at line 1785 of file core_starmc1.h.
| #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) |
FPCCR: processor mode active bit Mask
Definition at line 1786 of file core_starmc1.h.
| #define FPU_FPCCR_S_Pos 2U |
FPCCR: Security status of the FP context bit Position
Definition at line 1788 of file core_starmc1.h.
| #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) |
FPCCR: Security status of the FP context bit Mask
Definition at line 1789 of file core_starmc1.h.
| #define FPU_FPCCR_USER_Pos 1U |
FPCCR: privilege level bit Position
Definition at line 1791 of file core_starmc1.h.
| #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) |
FPCCR: privilege level bit Mask
Definition at line 1792 of file core_starmc1.h.
| #define FPU_FPCCR_LSPACT_Pos 0U |
FPCCR: Lazy state preservation active bit Position
Definition at line 1794 of file core_starmc1.h.
| #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) |
FPCCR: Lazy state preservation active bit Mask
Definition at line 1795 of file core_starmc1.h.
| #define FPU_FPCAR_ADDRESS_Pos 3U |
FPCAR: ADDRESS bit Position
Definition at line 1798 of file core_starmc1.h.
| #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) |
FPCAR: ADDRESS bit Mask
Definition at line 1799 of file core_starmc1.h.
| #define FPU_FPDSCR_AHP_Pos 26U |
FPDSCR: AHP bit Position
Definition at line 1802 of file core_starmc1.h.
| #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) |
FPDSCR: AHP bit Mask
Definition at line 1803 of file core_starmc1.h.
| #define FPU_FPDSCR_DN_Pos 25U |
FPDSCR: DN bit Position
Definition at line 1805 of file core_starmc1.h.
| #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) |
FPDSCR: DN bit Mask
Definition at line 1806 of file core_starmc1.h.
| #define FPU_FPDSCR_FZ_Pos 24U |
FPDSCR: FZ bit Position
Definition at line 1808 of file core_starmc1.h.
| #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) |
FPDSCR: FZ bit Mask
Definition at line 1809 of file core_starmc1.h.
| #define FPU_FPDSCR_RMode_Pos 22U |
FPDSCR: RMode bit Position
Definition at line 1811 of file core_starmc1.h.
| #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) |
FPDSCR: RMode bit Mask
Definition at line 1812 of file core_starmc1.h.
| #define FPU_MVFR0_FP_rounding_modes_Pos 28U |
MVFR0: FP rounding modes bits Position
Definition at line 1815 of file core_starmc1.h.
| #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) |
MVFR0: FP rounding modes bits Mask
Definition at line 1816 of file core_starmc1.h.
| #define FPU_MVFR0_Short_vectors_Pos 24U |
MVFR0: Short vectors bits Position
Definition at line 1818 of file core_starmc1.h.
| #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) |
MVFR0: Short vectors bits Mask
Definition at line 1819 of file core_starmc1.h.
| #define FPU_MVFR0_Square_root_Pos 20U |
MVFR0: Square root bits Position
Definition at line 1821 of file core_starmc1.h.
| #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) |
MVFR0: Square root bits Mask
Definition at line 1822 of file core_starmc1.h.
| #define FPU_MVFR0_Divide_Pos 16U |
MVFR0: Divide bits Position
Definition at line 1824 of file core_starmc1.h.
| #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) |
MVFR0: Divide bits Mask
Definition at line 1825 of file core_starmc1.h.
| #define FPU_MVFR0_FP_excep_trapping_Pos 12U |
MVFR0: FP exception trapping bits Position
Definition at line 1827 of file core_starmc1.h.
| #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) |
MVFR0: FP exception trapping bits Mask
Definition at line 1828 of file core_starmc1.h.
| #define FPU_MVFR0_Double_precision_Pos 8U |
MVFR0: Double-precision bits Position
Definition at line 1830 of file core_starmc1.h.
| #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) |
MVFR0: Double-precision bits Mask
Definition at line 1831 of file core_starmc1.h.
| #define FPU_MVFR0_Single_precision_Pos 4U |
MVFR0: Single-precision bits Position
Definition at line 1833 of file core_starmc1.h.
| #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) |
MVFR0: Single-precision bits Mask
Definition at line 1834 of file core_starmc1.h.
| #define FPU_MVFR0_A_SIMD_registers_Pos 0U |
MVFR0: A_SIMD registers bits Position
Definition at line 1836 of file core_starmc1.h.
| #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) |
MVFR0: A_SIMD registers bits Mask
Definition at line 1837 of file core_starmc1.h.
| #define FPU_MVFR1_FP_fused_MAC_Pos 28U |
MVFR1: FP fused MAC bits Position
Definition at line 1840 of file core_starmc1.h.
| #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) |
MVFR1: FP fused MAC bits Mask
Definition at line 1841 of file core_starmc1.h.
| #define FPU_MVFR1_FP_HPFP_Pos 24U |
MVFR1: FP HPFP bits Position
Definition at line 1843 of file core_starmc1.h.
| #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) |
MVFR1: FP HPFP bits Mask
Definition at line 1844 of file core_starmc1.h.
| #define FPU_MVFR1_D_NaN_mode_Pos 4U |
MVFR1: D_NaN mode bits Position
Definition at line 1846 of file core_starmc1.h.
| #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) |
MVFR1: D_NaN mode bits Mask
Definition at line 1847 of file core_starmc1.h.
| #define FPU_MVFR1_FtZ_mode_Pos 0U |
MVFR1: FtZ mode bits Position
Definition at line 1849 of file core_starmc1.h.
| #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) |
MVFR1: FtZ mode bits Mask
Definition at line 1850 of file core_starmc1.h.
| #define FPU_MVFR2_FPMisc_Pos 4U |
MVFR2: FPMisc bits Position
Definition at line 1853 of file core_starmc1.h.
| #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) |
MVFR2: FPMisc bits Mask
Definition at line 1854 of file core_starmc1.h.
| #define DCB_DHCSR_DBGKEY_Pos 16U |
DCB DHCSR: Debug key Position
Definition at line 1884 of file core_starmc1.h.
| #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) |
DCB DHCSR: Debug key Mask
Definition at line 1885 of file core_starmc1.h.
| #define DCB_DHCSR_S_RESTART_ST_Pos 26U |
DCB DHCSR: Restart sticky status Position
Definition at line 1887 of file core_starmc1.h.
| #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) |
DCB DHCSR: Restart sticky status Mask
Definition at line 1888 of file core_starmc1.h.
| #define DCB_DHCSR_S_RESET_ST_Pos 25U |
DCB DHCSR: Reset sticky status Position
Definition at line 1890 of file core_starmc1.h.
| #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) |
DCB DHCSR: Reset sticky status Mask
Definition at line 1891 of file core_starmc1.h.
| #define DCB_DHCSR_S_RETIRE_ST_Pos 24U |
DCB DHCSR: Retire sticky status Position
Definition at line 1893 of file core_starmc1.h.
| #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) |
DCB DHCSR: Retire sticky status Mask
Definition at line 1894 of file core_starmc1.h.
| #define DCB_DHCSR_S_SDE_Pos 20U |
DCB DHCSR: Secure debug enabled Position
Definition at line 1896 of file core_starmc1.h.
| #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) |
DCB DHCSR: Secure debug enabled Mask
Definition at line 1897 of file core_starmc1.h.
| #define DCB_DHCSR_S_LOCKUP_Pos 19U |
DCB DHCSR: Lockup status Position
Definition at line 1899 of file core_starmc1.h.
| #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) |
DCB DHCSR: Lockup status Mask
Definition at line 1900 of file core_starmc1.h.
| #define DCB_DHCSR_S_SLEEP_Pos 18U |
DCB DHCSR: Sleeping status Position
Definition at line 1902 of file core_starmc1.h.
| #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) |
DCB DHCSR: Sleeping status Mask
Definition at line 1903 of file core_starmc1.h.
| #define DCB_DHCSR_S_HALT_Pos 17U |
DCB DHCSR: Halted status Position
Definition at line 1905 of file core_starmc1.h.
| #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) |
DCB DHCSR: Halted status Mask
Definition at line 1906 of file core_starmc1.h.
| #define DCB_DHCSR_S_REGRDY_Pos 16U |
DCB DHCSR: Register ready status Position
Definition at line 1908 of file core_starmc1.h.
| #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) |
DCB DHCSR: Register ready status Mask
Definition at line 1909 of file core_starmc1.h.
| #define DCB_DHCSR_C_SNAPSTALL_Pos 5U |
DCB DHCSR: Snap stall control Position
Definition at line 1911 of file core_starmc1.h.
| #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) |
DCB DHCSR: Snap stall control Mask
Definition at line 1912 of file core_starmc1.h.
| #define DCB_DHCSR_C_MASKINTS_Pos 3U |
DCB DHCSR: Mask interrupts control Position
Definition at line 1914 of file core_starmc1.h.
| #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) |
DCB DHCSR: Mask interrupts control Mask
Definition at line 1915 of file core_starmc1.h.
| #define DCB_DHCSR_C_STEP_Pos 2U |
DCB DHCSR: Step control Position
Definition at line 1917 of file core_starmc1.h.
| #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) |
DCB DHCSR: Step control Mask
Definition at line 1918 of file core_starmc1.h.
| #define DCB_DHCSR_C_HALT_Pos 1U |
DCB DHCSR: Halt control Position
Definition at line 1920 of file core_starmc1.h.
| #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) |
DCB DHCSR: Halt control Mask
Definition at line 1921 of file core_starmc1.h.
| #define DCB_DHCSR_C_DEBUGEN_Pos 0U |
DCB DHCSR: Debug enable control Position
Definition at line 1923 of file core_starmc1.h.
| #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) |
DCB DHCSR: Debug enable control Mask
Definition at line 1924 of file core_starmc1.h.
| #define DCB_DCRSR_REGWnR_Pos 16U |
DCB DCRSR: Register write/not-read Position
Definition at line 1927 of file core_starmc1.h.
| #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) |
DCB DCRSR: Register write/not-read Mask
Definition at line 1928 of file core_starmc1.h.
| #define DCB_DCRSR_REGSEL_Pos 0U |
DCB DCRSR: Register selector Position
Definition at line 1930 of file core_starmc1.h.
| #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) |
DCB DCRSR: Register selector Mask
Definition at line 1931 of file core_starmc1.h.
| #define DCB_DCRDR_DBGTMP_Pos 0U |
DCB DCRDR: Data temporary buffer Position
Definition at line 1934 of file core_starmc1.h.
| #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) |
DCB DCRDR: Data temporary buffer Mask
Definition at line 1935 of file core_starmc1.h.
| #define DCB_DEMCR_TRCENA_Pos 24U |
DCB DEMCR: Trace enable Position
Definition at line 1938 of file core_starmc1.h.
| #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) |
DCB DEMCR: Trace enable Mask
Definition at line 1939 of file core_starmc1.h.
| #define DCB_DEMCR_MONPRKEY_Pos 23U |
DCB DEMCR: Monitor pend req key Position
Definition at line 1941 of file core_starmc1.h.
| #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) |
DCB DEMCR: Monitor pend req key Mask
Definition at line 1942 of file core_starmc1.h.
| #define DCB_DEMCR_UMON_EN_Pos 21U |
DCB DEMCR: Unprivileged monitor enable Position
Definition at line 1944 of file core_starmc1.h.
| #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) |
DCB DEMCR: Unprivileged monitor enable Mask
Definition at line 1945 of file core_starmc1.h.
| #define DCB_DEMCR_SDME_Pos 20U |
DCB DEMCR: Secure DebugMonitor enable Position
Definition at line 1947 of file core_starmc1.h.
| #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) |
DCB DEMCR: Secure DebugMonitor enable Mask
Definition at line 1948 of file core_starmc1.h.
| #define DCB_DEMCR_MON_REQ_Pos 19U |
DCB DEMCR: Monitor request Position
Definition at line 1950 of file core_starmc1.h.
| #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) |
DCB DEMCR: Monitor request Mask
Definition at line 1951 of file core_starmc1.h.
| #define DCB_DEMCR_MON_STEP_Pos 18U |
DCB DEMCR: Monitor step Position
Definition at line 1953 of file core_starmc1.h.
| #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) |
DCB DEMCR: Monitor step Mask
Definition at line 1954 of file core_starmc1.h.
| #define DCB_DEMCR_MON_PEND_Pos 17U |
DCB DEMCR: Monitor pend Position
Definition at line 1956 of file core_starmc1.h.
| #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) |
DCB DEMCR: Monitor pend Mask
Definition at line 1957 of file core_starmc1.h.
| #define DCB_DEMCR_MON_EN_Pos 16U |
DCB DEMCR: Monitor enable Position
Definition at line 1959 of file core_starmc1.h.
| #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) |
DCB DEMCR: Monitor enable Mask
Definition at line 1960 of file core_starmc1.h.
| #define DCB_DEMCR_VC_SFERR_Pos 11U |
DCB DEMCR: Vector Catch SecureFault Position
Definition at line 1962 of file core_starmc1.h.
| #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) |
DCB DEMCR: Vector Catch SecureFault Mask
Definition at line 1963 of file core_starmc1.h.
| #define DCB_DEMCR_VC_HARDERR_Pos 10U |
DCB DEMCR: Vector Catch HardFault errors Position
Definition at line 1965 of file core_starmc1.h.
| #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) |
DCB DEMCR: Vector Catch HardFault errors Mask
Definition at line 1966 of file core_starmc1.h.
| #define DCB_DEMCR_VC_INTERR_Pos 9U |
DCB DEMCR: Vector Catch interrupt errors Position
Definition at line 1968 of file core_starmc1.h.
| #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) |
DCB DEMCR: Vector Catch interrupt errors Mask
Definition at line 1969 of file core_starmc1.h.
| #define DCB_DEMCR_VC_BUSERR_Pos 8U |
DCB DEMCR: Vector Catch BusFault errors Position
Definition at line 1971 of file core_starmc1.h.
| #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) |
DCB DEMCR: Vector Catch BusFault errors Mask
Definition at line 1972 of file core_starmc1.h.
| #define DCB_DEMCR_VC_STATERR_Pos 7U |
DCB DEMCR: Vector Catch state errors Position
Definition at line 1974 of file core_starmc1.h.
| #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) |
DCB DEMCR: Vector Catch state errors Mask
Definition at line 1975 of file core_starmc1.h.
| #define DCB_DEMCR_VC_CHKERR_Pos 6U |
DCB DEMCR: Vector Catch check errors Position
Definition at line 1977 of file core_starmc1.h.
| #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) |
DCB DEMCR: Vector Catch check errors Mask
Definition at line 1978 of file core_starmc1.h.
| #define DCB_DEMCR_VC_NOCPERR_Pos 5U |
DCB DEMCR: Vector Catch NOCP errors Position
Definition at line 1980 of file core_starmc1.h.
| #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) |
DCB DEMCR: Vector Catch NOCP errors Mask
Definition at line 1981 of file core_starmc1.h.
| #define DCB_DEMCR_VC_MMERR_Pos 4U |
DCB DEMCR: Vector Catch MemManage errors Position
Definition at line 1983 of file core_starmc1.h.
| #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) |
DCB DEMCR: Vector Catch MemManage errors Mask
Definition at line 1984 of file core_starmc1.h.
| #define DCB_DEMCR_VC_CORERESET_Pos 0U |
DCB DEMCR: Vector Catch Core reset Position
Definition at line 1986 of file core_starmc1.h.
| #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) |
DCB DEMCR: Vector Catch Core reset Mask
Definition at line 1987 of file core_starmc1.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position
Definition at line 1990 of file core_starmc1.h.
| #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask
Definition at line 1991 of file core_starmc1.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U |
DCB DAUTHCTRL: Secure non-invasive debug enable select Position
Definition at line 1993 of file core_starmc1.h.
| #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) |
DCB DAUTHCTRL: Secure non-invasive debug enable select Mask
Definition at line 1994 of file core_starmc1.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U |
DCB DAUTHCTRL: Internal Secure invasive debug enable Position
Definition at line 1996 of file core_starmc1.h.
| #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure invasive debug enable Mask
Definition at line 1997 of file core_starmc1.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U |
DCB DAUTHCTRL: Secure invasive debug enable select Position
Definition at line 1999 of file core_starmc1.h.
| #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) |
DCB DAUTHCTRL: Secure invasive debug enable select Mask
Definition at line 2000 of file core_starmc1.h.
| #define DCB_DSCSR_CDSKEY_Pos 17U |
DCB DSCSR: CDS write-enable key Position
Definition at line 2003 of file core_starmc1.h.
| #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) |
DCB DSCSR: CDS write-enable key Mask
Definition at line 2004 of file core_starmc1.h.
| #define DCB_DSCSR_CDS_Pos 16U |
DCB DSCSR: Current domain Secure Position
Definition at line 2006 of file core_starmc1.h.
| #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) |
DCB DSCSR: Current domain Secure Mask
Definition at line 2007 of file core_starmc1.h.
| #define DCB_DSCSR_SBRSEL_Pos 1U |
DCB DSCSR: Secure banked register select Position
Definition at line 2009 of file core_starmc1.h.
| #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) |
DCB DSCSR: Secure banked register select Mask
Definition at line 2010 of file core_starmc1.h.
| #define DCB_DSCSR_SBRSELEN_Pos 0U |
DCB DSCSR: Secure banked register select enable Position
Definition at line 2012 of file core_starmc1.h.
| #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) |
DCB DSCSR: Secure banked register select enable Mask
Definition at line 2013 of file core_starmc1.h.
| #define DIB_DLAR_KEY_Pos 0U |
DIB DLAR: KEY Position
Definition at line 2039 of file core_starmc1.h.
| #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) |
DIB DLAR: KEY Mask
Definition at line 2040 of file core_starmc1.h.
| #define DIB_DLSR_nTT_Pos 2U |
DIB DLSR: Not thirty-two bit Position
Definition at line 2043 of file core_starmc1.h.
| #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) |
DIB DLSR: Not thirty-two bit Mask
Definition at line 2044 of file core_starmc1.h.
| #define DIB_DLSR_SLK_Pos 1U |
DIB DLSR: Software Lock status Position
Definition at line 2046 of file core_starmc1.h.
| #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) |
DIB DLSR: Software Lock status Mask
Definition at line 2047 of file core_starmc1.h.
| #define DIB_DLSR_SLI_Pos 0U |
DIB DLSR: Software Lock implemented Position
Definition at line 2049 of file core_starmc1.h.
| #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) |
DIB DLSR: Software Lock implemented Mask
Definition at line 2050 of file core_starmc1.h.
| #define DIB_DAUTHSTATUS_SNID_Pos 6U |
DIB DAUTHSTATUS: Secure Non-invasive Debug Position
Definition at line 2053 of file core_starmc1.h.
| #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) |
DIB DAUTHSTATUS: Secure Non-invasive Debug Mask
Definition at line 2054 of file core_starmc1.h.
| #define DIB_DAUTHSTATUS_SID_Pos 4U |
DIB DAUTHSTATUS: Secure Invasive Debug Position
Definition at line 2056 of file core_starmc1.h.
| #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) |
DIB DAUTHSTATUS: Secure Invasive Debug Mask
Definition at line 2057 of file core_starmc1.h.
| #define DIB_DAUTHSTATUS_NSNID_Pos 2U |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position
Definition at line 2059 of file core_starmc1.h.
| #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask
Definition at line 2060 of file core_starmc1.h.
| #define DIB_DAUTHSTATUS_NSID_Pos 0U |
DIB DAUTHSTATUS: Non-secure Invasive Debug Position
Definition at line 2062 of file core_starmc1.h.
| #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) |
DIB DAUTHSTATUS: Non-secure Invasive Debug Mask
Definition at line 2063 of file core_starmc1.h.
| #define DIB_DDEVARCH_ARCHITECT_Pos 21U |
DIB DDEVARCH: Architect Position
Definition at line 2066 of file core_starmc1.h.
| #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) |
DIB DDEVARCH: Architect Mask
Definition at line 2067 of file core_starmc1.h.
| #define DIB_DDEVARCH_PRESENT_Pos 20U |
DIB DDEVARCH: DEVARCH Present Position
Definition at line 2069 of file core_starmc1.h.
| #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) |
DIB DDEVARCH: DEVARCH Present Mask
Definition at line 2070 of file core_starmc1.h.
| #define DIB_DDEVARCH_REVISION_Pos 16U |
DIB DDEVARCH: Revision Position
Definition at line 2072 of file core_starmc1.h.
| #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) |
DIB DDEVARCH: Revision Mask
Definition at line 2073 of file core_starmc1.h.
| #define DIB_DDEVARCH_ARCHVER_Pos 12U |
DIB DDEVARCH: Architecture Version Position
Definition at line 2075 of file core_starmc1.h.
| #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) |
DIB DDEVARCH: Architecture Version Mask
Definition at line 2076 of file core_starmc1.h.
| #define DIB_DDEVARCH_ARCHPART_Pos 0U |
DIB DDEVARCH: Architecture Part Position
Definition at line 2078 of file core_starmc1.h.
| #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) |
DIB DDEVARCH: Architecture Part Mask
Definition at line 2079 of file core_starmc1.h.
| #define DIB_DDEVTYPE_SUB_Pos 4U |
DIB DDEVTYPE: Sub-type Position
Definition at line 2082 of file core_starmc1.h.
| #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) |
DIB DDEVTYPE: Sub-type Mask
Definition at line 2083 of file core_starmc1.h.
| #define DIB_DDEVTYPE_MAJOR_Pos 0U |
DIB DDEVTYPE: Major type Position
Definition at line 2085 of file core_starmc1.h.
| #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) |
DIB DDEVTYPE: Major type Mask
Definition at line 2086 of file core_starmc1.h.
| #define _VAL2FLD | ( | field, | |
| value ) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
Definition at line 2105 of file core_starmc1.h.
| #define _FLD2VAL | ( | field, | |
| value ) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
Definition at line 2113 of file core_starmc1.h.
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
Definition at line 2126 of file core_starmc1.h.
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
Definition at line 2127 of file core_starmc1.h.
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
Definition at line 2128 of file core_starmc1.h.
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
Definition at line 2129 of file core_starmc1.h.
| #define DCB_BASE (0xE000EDF0UL) |
DCB Base Address
Definition at line 2130 of file core_starmc1.h.
| #define DIB_BASE (0xE000EFB0UL) |
DIB Base Address
Definition at line 2131 of file core_starmc1.h.
| #define EMSS_BASE (0xE001E000UL) |
Enhanced Memory SubSystem Base Address
Definition at line 2132 of file core_starmc1.h.
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
Definition at line 2134 of file core_starmc1.h.
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
Definition at line 2135 of file core_starmc1.h.
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
Definition at line 2136 of file core_starmc1.h.
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
Definition at line 2138 of file core_starmc1.h.
SCB configuration struct
Definition at line 2139 of file core_starmc1.h.
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
Definition at line 2140 of file core_starmc1.h.
NVIC configuration struct
Definition at line 2141 of file core_starmc1.h.
ITM configuration struct
Definition at line 2142 of file core_starmc1.h.
DWT configuration struct
Definition at line 2143 of file core_starmc1.h.
TPI configuration struct
Definition at line 2144 of file core_starmc1.h.
DCB configuration struct
Definition at line 2145 of file core_starmc1.h.
DIB configuration struct
Definition at line 2146 of file core_starmc1.h.
Ehanced MSS Registers struct
Definition at line 2147 of file core_starmc1.h.
| #define MPU_BASE (SCS_BASE + 0x0D90UL) |
Memory Protection Unit
Definition at line 2150 of file core_starmc1.h.
Memory Protection Unit
Definition at line 2151 of file core_starmc1.h.
| #define FPU_BASE (SCS_BASE + 0x0F30UL) |
Floating Point Unit
Definition at line 2159 of file core_starmc1.h.
Floating Point Unit
Definition at line 2160 of file core_starmc1.h.